- ページ 8

デスクトップ HP 226824-001 - ProLiant - ML750のPDF 概要をオンラインで閲覧またはダウンロードできます。HP 226824-001 - ProLiant - ML750 20 ページ。 Visualization and acceleration in hp proliant servers
HP 226824-001 - ProLiant - ML750 にも： よくある質問 (4 ページ), 実施マニュアル (35 ページ), テクニカル・ホワイトペーパー (12 ページ), ファームウェア・アップデート (9 ページ), 実施マニュアル (26 ページ), 導入マニュアル (22 ページ), トラブルシューティングマニュアル (18 ページ), 実施マニュアル (11 ページ), インストレーション・マニュアル (2 ページ), 設定マニュアル (2 ページ), 導入マニュアル (19 ページ), 更新マニュアル (9 ページ), 更新マニュアル (16 ページ), 導入マニュアル (12 ページ), 導入マニュアル (10 ページ), 技術概要 (9 ページ)

ページを印刷する
HP 226824-001 - ProLiant - ML750 概要

DIMM Configurations

Single-sided and double-sided DIMMs

Each DRAM chip on a DIMM provides either 4 bits or 8 bits of a 64-bit data word. Chips that
provide 4 bits are called x4 (by 4), and chips that provide 8 bits are called x8 (by 8). It takes eight
x8 chips or sixteen x4 chips to make a 64-bit word, so at least eight chips are located on one or both
sides of a DIMM. However, a standard DIMM has enough room to hold a ninth chip on each side.
The ninth chip is used to store 4 bits or 8 bits of Error Correction Code, or ECC (see "Parity and ECC
DIMMs" sidebar on next page).
An ECC DIMM with all nine DRAM chips on one side is called single-sided, and an ECC DIMM with
nine DRAM chips on each side is called double-sided (Figure 7). A single-sided x8 ECC DIMM and a
double-sided x4 ECC DIMM each create a single block of 72 bits (64 bits plus 8 ECC bits). In both
cases, a single chip-select signal from the chipset is used to activate all the chips on the DIMM. In
contrast, a double-sided x8 DIMM (bottom illustration) requires two chip-select signals to access two
72-bit blocks on two sets of DRAM chips.

Single-rank, dual-rank, and quad-rank DIMMs

In addition to single-sided and double-sided configurations, DIMMs are classified as single-rank or
dual-rank. A memory rank is defined as an area or block of 64-bits created by using some or all of
the DRAM chips on a DIMM. For an ECC DIMM, a memory rank is a block of 72 data bits (64 bits
plus 8 ECC bits).
A single-rank ECC DIMM (x4 or x8) uses all of its DRAM chips to create a single block of 72 bits, and
all the chips are activated by one chip-select signal from the chipset (top two illustrations in Figure 7).
A dual-rank ECC DIMM produces two 72-bit blocks from two sets of DRAM chips on the DIMM,
requiring two chip-select signals. The chip-select signals are staggered so that both sets of DRAM
chips do not contend for the memory bus at the same time. Quad-rank DIMMs with ECC produces
four 72-bit blocks from four sets of DRAM chips on the DIMM, requiring four chip-select signals. Like
the dual-rank DIMMs, the memory controller staggers the chip-select signals to prevent the four sets of
DRAM chips from contending for the memory bus at the same time.
Figure 7. Single-sided and double-sided DDR SDRAM DIMMs and corresponding DIMM rank
8