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XC95108 CPLD
The block diagram of the DXC95 board shows all connections
between the CPLD and the devices on the board. All CPLD pin
connections are shown in the table.
The CPLD device can be configured using the Xilinx JTAG tools
and a parallel cable connecting the DXC95 board and the host
computer.
For further information on the XC95108 CPLD, please see the
Xilinx data sheets available at the Xilinx website (www.xilinx.com).
DB-25 parallel port
JTAG
Clock
4
Xilinx XC95108 CPLD
30
Expansion F
DXC95 CPLD circuit block diagram
Rev: May 7, 2002
Push
LED
button
37
Expansion E
1
www.digilentinc.com
Digilent, Inc.
Pin
Function
Pin
1
LED1
43
2
BTN1
44
3
E29
45
4
E28
46
5
E27
47
6
E26
48
7
E25
49
8
GND
50
9
MCLK
51
10
GCLK2
52
11
E23
53
12
GCK3
54
13
E21
55
14
E20
56
15
E19
57
16
GND
58
17
E18
59
18
E17
60
19
E16
61
20
E15
62
21
E14
63
22
VCCIO
64
23
E13
65
24
E12
66
25
E11
67
26
E10
68
27
GND
69
28
TDI
70
29
TMS
71
30
TCK
72
31
E9
73
32
E8
74
33
E7
75
34
E6
76
35
E5
77
36
E4
78
37
F40
79
38
VCCINT
80
39
F39
81
40
F38
82
41
F37
83
42
GND
84
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Function
F36
F35
F34
F33
F32
F31
GND
F30
F29
F28
F27
F26
F25
F24
F23
F22
TDO
GND
F21
F20
F19
VCCIO
F18
F17
F16
F15
F14
F13
F12
F11
VCCINT
GSR
F10
GTS1
GTS2
VCCINT
F9
F8
F7
F6
F5
F4