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ページを印刷するAtlys Reference Manual
Atlys power supplies are enabled by a logic-level switch (SW8). A power-good LED (LD15), driven by
the wired-OR of all the "power good" outputs on the supplies, indicates that all supplies are operating
within 10% of nominal.
A load switch (the FDC6330 at IC17) passes the input voltage VU to the Vswt node whenever the
power switch (SW8) is enabled. Vswt is assumed to be 5V, and is used by many systems on the
board including the HDMI ports, I2C bus, and USB host. Vswt is also available at expansion
connectors, so that any connected boards can be turned off along with the Atlys board.
DDR2 Memory
A single 1Gbyte DDR2 memory chip is driven from the memory controller block in the Spartan-6
FGPA. The DDR2 device, a Micron MT47H64M16-25E or equivalent, provides a 16-bit bus and 64M
locations. The Atlys board has been tested for DDR2 operation at up to an 800MHz data rate.
The DDR2 interface follows the pinout and routing guidelines specified in the Xilinx Memory Interface
Generator (MIG) User Guide. The interface supports SSTL18 signaling, and all address, data, clocks,
and control signals are delay-matched and impedance-controlled. Address and control signals are
terminated through 47-ohm resistors to a 0.9V V
(ODT) feature of the DDR2 chip. Two well-matched DDR2 clock signal pairs are provided so the DDR
can be driven with low-skew clocks from the FPGA.
Doc: 502-178
, and data signals use the On-Die-Termination
TT
Address
A12: G6
A4: F3
A11: D3
A3: L7
A10: F4
A2: H5
A9: D1
A1: J6
A8: D2
A0: J7
A7: H6
A6: H3
A5: H4
Data
D15: U1
D7: J1
D14: U2
D6: J3
D13: T1
D5: H1
D12: T2
D4: H2
D11: N1
D3: K1
D10: N2
D2: K2
D9: M1
D1: L1
D8: M3
D0: L2
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