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ソフトウェア Epson SED1560 SeriesのPDF テクニカル・マニュアルをオンラインで閲覧またはダウンロードできます。Epson SED1560 Series 40 ページ。 Lcd driver with ram

SED1520 Series

Common Timing Generator Circuit

Generates common timing signals and FR frame signals

from the CL basic clock. The 1/16 or 1/32 duty (for

SED1520) or 1/8 or 1/16 duty (for SED1522) can be

selected by the Duty Select command. If the 1/32 duty is

selected for the SED1520 and 1/16 duty is selected for the

SED1522, the 1/32 and 1/16 duties are provided by two

chips consisting of the master and slave chips in the

common multi-chip mode.

SED1520

FR signal

(Master output)

Master Common

Slave Common

SED1522

FR signal

(Master output)

Master Common

Slave Common

This latch stores one line of display data for use by the

LCD driver interface circuitry. The output of this latch

is controlled by the Display ON/OFF and Static Drive

ON/OFF commands.

The LCD driver circuitry generates the 80 4-level signals

used to drive the LCD panel, using output from the

display data latch and the common timing generator

circuitry.

2–10

14 15

16 17

This circuit generates the internal display timing signal

using the basic clock, CL, and the frame signals, FR.

FR is used to generate the dual frame AC-drive wave-

form (type B drive) and to lock the line counter and

common timing generator to the system frame rate.

CL is used to lock the line counter to the system line scan

rate. If a system uses both SED1520s or SED1522 and

SED1521s they must have the same CL frequency rating.

EPSON

30 31

16 17

14 15