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7 . DIGITAL CIRCUIT
The digital circuit performs various operations such as a
format conversion (enlargement, reduction) which
converts an input signal into a XGA signal, automatic
adjustments, sync signal generation, etc.
The operations are described below by referring to each
c i r c u i t b l o c k .
7-1. Input Side PLL Circuit
In the digital circuit, the PLL circuit generates clock
signals by using the H sync signal entered.
When RGB signals are entered, clock signals precisely
synchronized with the pixel clock of the personal computer
must be generated. To obtain this precise clock signals,
an ultra-high speed, low jitter PLL IC, CXA3106AQ
(QD026), is used in this unit. The CXA3106AQ is a PLL
IC containing a division circuit and a loop filter and
generates, by controlling through a serial bus, clock
signals up to 160 MHz synchronized with the input
signal entered the SYNC (pin 9). The IC provides TTL
level clock signals (pins 20-23) and PECL level clock
signals (pins 29-32). Moreover, the IC provides clock
signals divided by 2 (TTL: pin 20-21, PECL: pin 29-30).
The PECL level clock signals are of differential output.
On the other hand, when a video signal is entered, a PLL
IC, TLC2932 (QD024) with fine tracking characteristics,
is used to follow signals containing jitter from a VTR,
etc. TLC2932 is connected to the external VCO (pin 5) of
QD026 and the bus control determines which one of ICs
i s t o b e s e l e c t e d .
7-2. Output Side PLL Circuit
The LC panel needs a pixel clock input of approx. 65
MHz. The output side PLL circuit generates the clock
signal of approx. 65 MHz from the system clock (In case
of NTSC and PAL MODE, the output side PLL circuit
generates the clock signal of 67 MHz).
The output side PLL circuit also uses the CXA3106AQ
(QD027).
7-3. AD Converter Circuit
The CXA3026AQ (QD201, QD301, QD401) is an 8 bit
A/D converter which can operate up to max. 140 MHz.
The A/D converter converts voltages across VRB (pin 2)
and VRT (pin 11) into a digital signal. In this model, the
VRB is set to 1.5V and VRT = 3.0V. So, the amplitude of
input signal is 1.5V – 3.0V.
The converter also employs a demultiplex output system.
As the maximum conversion speed of the A/D converter
is very high speed of 140 MHz, the process circuit just
following this can not follow if the output is applied
directly. By dividing the 8 bit signal of max. 140 MHz
into two 8 bit signals, the signals demultiplexed are
handled as signals of max. 70 MHz. In this way, the
signals are processed as 8 bit
the D/A converter input (multiplex circuit).
7-4. Format Conversion, Enlargement,
Reduction Circuits
The format conversion, enlargement, and reduction are
carried out by IP00C702 (QD203, QD303, QD403). The
IC stores the input signals in SG-RAMs (QD202,
QD302, QD402) and performs the enlargement and
reduction by using two-dimensional digital filters. Since
a picture is once stored in a memory, it can be output at a
timing not related to the input signal. The resolution of
LC panel used in this model is of XGA (1024
the signals are output in the XGA format (fv = 60 Hz).
7-5. Multiplex Circuit
The signal following the A/D converter is processed as a
x 2 to process the high-speed signal, but
signal of 8 bit
the signal is converted into a signal of 8 bit
multiplex circuit. As the signal in this part is converted
into a 65 MHz signal by the format conversion circuit, a
signal of 32.5 MHz, 8 bit
8 bit signal in actually, thus allowing the operation with
sufficient margin.
7-6. D/A Converter Circuit
TDA8872H (QD601) is a 3 CH, 8 bit D/A converter and
provides 1 V(p-p) output.
7-1
x 2 signals up to just before
x 768), all
x 1 in the
x 2 is converted into a 65 MHz,