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DDR4 + Intel® Optane™ Persistent Memory 200 Series
Slot
Channel 1
Channel 0
(ch F)
DDR4
+BPS
D11
D12
D9
(Mode)
4+4
BPS
DDR4
(1LM+AD,
BPS
DDR4
MM)
DDR4
DDR4
DDR4
DDR4
DDR4
6+1
BPS
DDR4
(1LM+AD)
DDR4
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
8+1
DDR4
DDR4
(1LM+AD)
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
8+4
DDR4
DDR4
(1LM+AD,
BPS
DDR4
DDR4
MM)
BPS
DDR4
DDR4
8+8
(1LM+AD,
BPS
DDR4
DDR4
MM)
BPS
DDR4
12+2
DDR4
DDR4
DDR4
(1LM+AD)
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
Important
Important
•
There should be at least one DDR4 DIMM per socket.
•
If only one DIMM is populated in a channel, then populate it in the slot furthest away from CPU of that
channel.
•
Always populate the DIMM with the higher electrical loading on a channel in DIMM0 followed by DIMM1.
•
ICX Channel 0's on each memory controller (A/E/C/G) must be populated with same total capacity per
channel (if populated).
•
ICX Channel 1's on each memory controller (B/F/D/H) must be populated with same total capacity per
channel (if populated).
•
For MM, Near Memory/Far Memory ratio is between 1:4 and 1:16.
•
Matrix targets configs for optimized PMem to DDR4 cache ratio in MM modes.
•
For a bring-up purpose, (1 DDR4 and 1 PMem) per socket or (2 DDR4 and 1 PMem) per socket are
allowed for Power-On/Debug, which is not part of volume validation.
•
Reference platform mechanically can't support PMem configs with PMem in the outside slot adjacent to
the other processors' outer slot.
•
Mirroring only applies to 1LM mode.
•
SNC and Hemi/UBC apply only to 1LM, MM volatile region.
•
Rank sparing, ADDDC, channel mirroring, hemisphere modes, and 2LM are not supported with Intel
SGX.
•
8+8 configs: PMem ADx1 (non-interleave) supports fall back to each 8+x config with PMem failure.
Channel 1
Channel 0
(ch E)
(ch H)
(ch G)
D10
D15
D16
D13
BPS
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
BPS
DDR4
DDR4
BPS
BPS
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
BPS
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
Channel 0
Channel 1
(ch C)
(ch D)
D14
D6
D5
D8
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
C
DDR4
P
BPS
DDR4
U
DDR4
BPS
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
BPS
BPS
DDR4
BPS
DDR4
BPS
BPS
DDR4
BPS
DDR4
BPS
BPS
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
MS-S2201, MS-S1201
Channel 0
Channel 1
(ch A)
(ch B)
D7
D2
D1
D4
D3
BPS
BPS
DDR4
BPS
DDR4
DDR4
BPS
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
BPS
BPS
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
BPS
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
DDR4
®
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