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A
B
DP-U50
I
PRINTED CIRCUIT BOARD (Foil side)
1
2
CENTER
LFE
AGND
RCH
LCH
+5A
+12V
+15V
AC DET
+5D SUB
3
T MUTE
SW MUTE
CLK
VOLCE2
PRT I
SP ON
A MUTE
POW
E_B
KEY0
+5S
LED A1
LED TU
+5M
CCBDI
FLCE
REM
4
5
E-28/J-26
6
C
DSP P.C.B.
(Lead Type Device)
5
8
1
4
1
8
8
1
5
4
5
4
20
11
1
10
AGND
RLCH
RRCH
14
15
14
15
AGND
AGND
+9V
1
28
1
28
-15V
DGND
+5D SW
T-FAULT
PHONE
DATA
VOLCE1
PRT DC
132
E
PS
121
160
1
120
E_A
P SW
89
LED PC
88
LED A2
/ICD
GNDD
CCBCLK
GNDD
81
40
80
41
40
21
1
57
20
1
56
25
48
29
28
24
1
D
E
1
15
ANALOG
30
16
PC IN
4
5
8
1
AUX 1 IN
AUX 2 IN
PRE OUT
2
DIGITAL
USB
1
COAX IN
PC
8
14
44
45
OPT IN
1
7
AUX 1
OPT IN
OPT OUT
84
U, C, A, B, G only
85
1
7
112
8
14
1
1
4
4
8
5
3
E-29/J-27
F
G
Point q (Pin 1 of IC417)
G
Semiconductor Location
V : 2V/div, H : 50 nsec/div
Ref. No. Location
Ref. No.
Location
DC, 1 : 1 probe
D413
C2
IC401
D5
D414
C2
IC406
C3
D415
C2
IC412
D3
D416
C2
IC413
C5
D417
C2
IC416
D5
D418
C2
IC417
C4
0V
D419
C2
IC418
D4
D420
C2
IC430
D3
D437
C5
IC432
C4
D440
D2
IC436
D5
D441
D2
IC438
C5
D442
D2
IC439
C3
D443
D2
IC440
C3
Point w (Pin 4 of IC430)
D444
D2
IC454
C2
D445
D2
IC458
C2
V : 1V/div, H : 50 nsec/div
D446
D2
IC471
D2
DC, 1 : 1 probe
D447
D2
IC473
D1
IC474
D2
IC475
D3
IC477
C2
IC478
D2
0V
Ref. No.
Location
Q401
D3
Q402
C2
Q403
C2
Q404
C2
Point e (Pin 74 of IC436)
Q405
C2
V : 2V/div, H : 0.1 µsec/div
Q410
C1
DC, 1 : 1 probe
Q411
C2
Q417
C1
Q418
C2
Q420
D3
Q421
D3
0V
Q423
D2
Q424
D2
Q427
D2
Q428
D2
Point r (Pin 47 of IC475)
V : 2V/div, H : 50 nsec/div
DC, 1 : 1 probe
0V
NOTE)
The DSP P.C.B. actually has a four-layer pattern structure (part face pattern, internal pattern
1, internal pattern 2 and solder face pattern) but it is shown as "part face pattern + solder
face pattern" in this diagram.
NOTE)
H