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Yamaha YST-MS55D にも： オーナーズマニュアル (15 ページ)
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- 1. Table of Contents
- 2. To Service Personnel
- 3. Front and Rear Panels
- 4. Specifications
- 5. Internal View
- 6. Disassembly Procedures
- 7. Usb Port Operation Check
- 8. Block Diagram
- 9. Printed Circuit Board
- 10. Printed Circuit Board
- 11. IC Data
- 12. Schematic Diagram
- 13. Schematic Diagram
- 14. Parts List
- 15. Parts List for Carbon Resistors
YST-MS50/YST-MS55D
IC DATA
IC201: UDA1321PS
Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)
1
GP2/DO
GP3/WSO
2
3
GP4/BCKO
4
SHTCB
NC
5
D–
6
7
D+
V
I
8
DD
TOP VIEW
VssI
9
10
VssE
V
E
11
DD
NC
12
13
VssX
14
XTAL1
XTAL2
15
V
X
16
DD
No.
Name
I/O
∗1
1
GP2/DO
∗1
2
GP3/WSO
∗1
3
GP4/BCKO
∗2
4
SHTCB
5
NC
Unconnected
6
D–
Negative
I/O
7
D+
Positive
I/O
8
V
I
Power supply
DD
9
VssI
Ground
10
VssE
Ground
11
V
E
Power supply
DD
12
NC
Unconnected
13
VssX
Ground
14
XTAL1
Input
15
XTAL2
Output
16
V
X
Power supply
DD
NOTE) ∗1 : Normally unconnected.
IC202: M24C02-BN6
2k 2.5V CMOS Serial
Electrically Erasable PROM
(EEPROM)
No.
Name
I/O Function
∗1
1
A0
∗1
2
A1
∗1
3
A2
4
Vss
Ground
NOTE) ∗1 : Normally connected to ground. ∗2 : Normally connected to power supply.
23
YST-MS55D
25
TC
20
RTCB
4
SHTCB
3
GP4/BCKO
2
GP3/WSO
1
GP2/DO
32
GP1/DI
27
GP0/BCKI
32
GP1/DI
29
GP5/WSI
31
SDA
30
SCL
29
GP5/WSI
28
NC
27
GP0/BCKI
26
RTCB
25
TC
24
VOUTL
23
V
O
DD
22
VssO
21
VOUTR
20
V
A
DD
24
VOUTL
19
VssA
13
VssX
18
Vref
14
XTAL1
17
NC
15
XTAL2
V
X
16
DD
Function
Data line of the differential
data bus common to the
USB-standard.
(for digital core)
(for digital I/O)
(for Crystal oscillator)
∗2 : Normally connected to ground.
1
A0
2
A1
TOP VIEW
A2
3
Vss
4
No.
Name
I/O
Function
8
Vcc
Power supply
∗2
7
WP
6
SCL
Serial clock (I
O
5
SDA
Serial data (I
I/O
D+
7
ANALOG FRONT-END
TEST
CONTROL
BLOCK
USB-PROCESSOR
DIGITAL I/O
FIFO REGISTERS
fs
SAMPLE
AUDIO FEATURE
FREQUENCY
PROCESSING DSP
GENERATOR
fs
UP-SAMPLE FILTER
64fs
VARIABLE HOLD REGISTER
128fs
3rd-ORDER
NOISE SHAPER
LEFT DAC
–
+
REFERENCE VOLTAGE
OSC
TIMING
No.
Name
I/O
∗1
32
GP1/DI
31
SDA
Serial data (I
I/O
30
SCL
Serial clock (I
I
∗1
29
GP5/WSI
28
NC
Unconnected
∗1
27
GP0/BCKI
∗2
26
RTCB
∗2
25
TC
24
VOUTL
Lch Output voltage
O
23
V
O
Power supply
DD
22
VssO
Ground
21
VOUTR
Rch output voltrage
O
20
V
A
Power supply
DD
19
VssA
Ground
18
Vref
Reference Voltage
O
17
NC
Unconnected
Vss
Vcc
WP
4
8
7
8
Vcc
7
WP
6
SCL
I/O
MEMORY
5
SDA
CONTROL
CONTROL
LOGIC
2
C-Bus)
2
C-Bus)
5
6
SDA SCL
D–
6
FOR ANALOG
MICRO-
CONTROLLER
FOR DIGITAL I/O
FOR DIGITAL CORE
RIGHT DAC
–
+
FOR OPE-AMP
18
Vref
Function
2
C-Bus)
2
C-Bus)
(for OPE-AMP.)
(for analog)
HV GENERATOR
EEPROM
ARRAY
XDEC
LOGIC
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
20
V
A
DD
19
VssA
30
SCL
31
SDA
11
V
E
DD
10
VssE
9
VssI
8
V
I
DD
21
VOUTR
23
V
O
DD
22
VssO