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i4000 - Quad M-module Carrier for VMEbus
5.2.3.

Control register

Control Register
7
RES
reset:
u
Write only
L2-L0 (Interrupt level, dummy bits)
The least significant 3-bit field of the register determines the level at which an
interrupt will be generated.
These three bits are NOT used in the i4000 interrupt controller since the interrupt
level for all the four modules is selected via dip switches. However to maintain
software compatibility with the A201 it is advisable to program these 3 bits with
the same interrupt level as the dip switches.
IRAC (Interrupt Auto-Clear)
If the IRAC is set (Bit 3), IRE (Bit 4) is cleared during an interrupt acknowledge
cycle responding to this request. This action of clearing IRE disables the module
interrupt request. To re-enable the module interrupt request associated with this
register, IRE must be set again by writing to the control register.
IRE (Interrupt enable)
This field (Bit 4) must be set (high level) to enable the module interrupt request
associated with the control register. Thus, if the module asserts IRQ and IRE is
cleared, no interrupt request to the VMEbus will be generated.
X/IN* (External/Internal)
Bit 5 of the control register determines the response of the i4000 interrupt
controller during an interrupt acknowledge cycle. If the X/IN* bit is clear (low
level) the Interrupt Controller will respond with vector data and a DTACK* signal,
i.e., an internal response. If X/IN* is set, the vector is not supplied and no DTACK*
is given by the Interrupt Controller, i.e., an external module should respond.
RESERVED
These two bits are not used in the current implementation of the Interrupt
Controller and reserved for future use.
AcQuisition Technology B.V.
P.O. Box 627, 5340 AP OSS, The Netherlands
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6
5
4
RES
X/IN
IRE
u
u
u
3
2
1
IRAC
L2
L1
u
u
u
Tel: +31 412 651055
Fax: +31 412 651050
page 15
0
L0
u