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RS232 connector for communication with a PC. These are described in detail below.

6.1. Target Chip and Connector J1

Please note that the square pad on the bottom side of the printed wiring may not correctly reflect the position of pin
1. Refer to the diagrams in this documentation for the correct location of J1 pin 1.
Pin-outs for the 18-pin DIP and 20 / 24-pin SOIC configurations the Cypress USB IC family are given in Table 3.
Note that not all chip pins are implemented on the emulation board. All other pins on connector J1 are test points,
and should not be connected to any other signal.
Pin
18-DIP
Name
Pin #
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
VSS
VCC
VPP
Xi
Xo
Cext
USB D+
USB D−
P1[7]
P1[6]
P1[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
* Not used on development system board
** Requires jumper JP1 to connect to +5V on the development system board (see Section 3.2)

6.2. J2 - Microcontroller Signals

For debug purposes, microcontroller interface signals are available at connector J2. Table 4 gives pin functions for
the signals, and Table 5 lists all signal locations on the J2 connector. Consult Figure 4 for the correct position of pin
CY3650 USB Development System User's Guide
Table 3: Target Chip Pins
20-SOIC
Pin #
15
17
16
18
17
19
18
20
4
4
3
3
2
2
1
1
6
7
11
12
7
8
9
10
10
11
8
9
13
14
12
13
-
-
-
-
-
-
-
-
-
15
-
6
14
16
5
5
24-SOIC
Pin #
Description
Port 0, Bit 7 (MSB)
21
Port 0, Bit 6
22
Port 0, Bit 5
23
Port 0, Bit 4
24
Port 0, Bit 3
4
Port 10, Bit 2
3
Port 0, Bit 1
2
Port 0, Bit 0 (LSB)
1
9
Ground
14
Positive Supply (+5V)
10
EPROM Supervoltage*
12
Oscillator input*
13
Oscillator output*
11
External RC wake-up
16
USB D+
15
USB D−
17
Port 1, Bit 7 (24p SOIC only)
8
Port 1, Bit 6 (24p SOIC only)
18
Port 1, Bit 5 (24p SOIC only)
7
Port 1, Bit 4 (24p SOIC only)
19
Port 1, Bit 3 (SOIC only)
6
Port 1, Bit 2 (SOIC only)
20
Port 1, Bit 1
5
Port 1, Bit 0 (LSB)
– 8 –
J1
Pin #
7
8
5
6
3
4
1
2
59,60
57**
*
*
*
43
42
41
15
16
13
14
11
12
9
10
Ver 2.4