- ページ 9
コンピュータ・ハードウェア Cypress Semiconductor CY2291のPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor CY2291 12 ページ。 Cypress three-pll general purpose eprom programmable clock generator specification sheet
ページを印刷するSwitching Characteristics, Industrial 3.3V
Parameter
Name
t
Output Enable
6
Time
t
Skew
7
t
CPUCLK Slew
8
[14]
t
Clock Jitter
9A
[14]
t
Clock Jitter
9B
[14]
t
Clock Jitter
9C
[14]
t
Clock Jitter
9D
t
Lock Time for
10A
CPLL
t
Lock Time for
10B
UPLL and SPLL
Slew Limits
Switching Waveforms
OUTPUT
OE
ALL
THREE-STATE
OUTPUTS
CLK
OUTPUT
RELATED
CLK
Document #: 38-07189 Rev. *C
(continued)
Description
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related outputs
12, 15]
Frequency transition rate
Peak-to-peak period jitter (t
9A
clock period (f
< 4 MHz)
OUT
Peak-to-peak period jitter (t
9B
< f
< 16 MHz)
OUT
Peak-to-peak period jitter
(16 MHz < f
< 50 MHz)
OUT
Peak-to-peak period jitter (f
OUT
Lock Time from Power Up
Lock Time from Power Up
CPU PLL Slew Limits
Figure 2. All Outputs, Duty Cycle and Rise/Fall Time
t
2
t
3
Figure 3. Output Three-State Timing
t
5
Figure 4. CLK Outputs Jitter and Skew
t
9A
t
7
[3,
Max. – t
min.),% of
9A
Max. – t
min.) (4 MHz
9B
> 50 MHz)
CY2291I
CY2291FI
t
1
t
4
[4]
CY2291
Min.
Typ.
Max.
10
15
< 0.25
0.5
1.0
20.0
< 0.5
1
< 0.7
1
< 400
500
< 250
350
< 25
50
< 0.25
1
8
66.6
8
60
t
6
Page 9 of 12
Unit
ns
ns
MHz/ms
%
ns
ps
ps
ms
ms
MHz
MHz
[+] Feedback