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Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62146DV30
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 7 µA
• Ultra low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Functional Description
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
Product Portfolio
Product
Min
CY62146EV30LL
2.2
Notes:
1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
Cypress Semiconductor Corporation
Document #: 38-05567 Rev. *C
[1]
®
) in
Speed
V
Range (V)
CC
[2]
Typ
Max
3.0
3.6
•
198 Champion Court
4-Mbit (256K x 16) Static RAM
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (IO
IO
) are placed in a high impedance state when:
15
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
• Write operation is active (CE LOW and WE LOW)
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW,
then data from IO pins (IO
location specified on the address pins (A
High Enable (BHE) is LOW, then data from IO pins (IO
through IO
) is written into the location specified on the
15
address pins (A
through A
0
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO
Byte High Enable (BHE) is LOW, then data from memory
appears on IO
to IO
8
15
complete description of read and write modes.
Operating I
(ns)
f = 1 MHz
[2]
Typ
Max
45 ns
2
2.5
,
•
San Jose
CY62146EV30 MoBL
through IO
), is written into the
0
7
through A
0
).
17
. See the
"Truth Table" on page 9
Power Dissipation
(mA)
CC
Standby I
f = f
max
[2]
[2]
Typ
Max
Typ
15
20
1
= V
, T
= 25°C.
CC
CC(typ)
A
CA 95134-1709
•
408-943-2600
Revised March 26, 2007
®
through
0
). If Byte
17
8
to IO
. If
0
7
for a
(µA)
SB2
Max
7