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コンピュータ・ハードウェア Cypress Semiconductor CY62147DV30のPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor CY62147DV30 13 ページ。 4-mbit (256k x 16) static ram
ページを印刷するCapacitance
(for all packages)
Parameter
C
Input Capacitance
IN
C
Output Capacitance
OUT
[10]
Thermal Resistance
Parameter
Description
Θ
Thermal Resistance
JA
(Junction to Ambient)
Θ
Thermal Resistance
JC
(Junction to Case)
AC Test Loads and Waveforms
V
CC
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
Parameters
R1
R2
R
TH
V
TH
Data Retention Characteristics
Parameter
Description
V
V
for Data Retention
DR
CC
I
Data Retention Current
CCDR
[10]
t
Chip Deselect to Data Retention
CDR
Time
[12]
t
Operation Recovery Time
R
Data Retention Waveform
V
CC
CE or
BHE.BLE
Notes:
10. Tested initially and after any design or process changes that may affect these parameters.
11. Test condition for the 45-ns part is a load capacitance of 30 pF.
12. Full device operation requires linear V
13. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05340 Rev. *F
[10]
Description
T
A
V
CC
Still Air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
[10]
R1
V
CC
GND
Rise Time = 1 V/ns
R2
Equivalent to:
2.50V
16667
15385
8000
1.20
(Over the Operating Range)
V
= 1.5V
CC
CE > V
– 0.2V,
CC
V
> V
– 0.2V or
IN
CC
V
< 0.2V
IN
[13]
DATA RETENTION MODE
V
CC(min)
t
CDR
> 100 µs or stable at V
ramp from V
to V
CC
DR
CC(min.)
Test Conditions
= 25°C, f = 1 MHz,
= V
CC(typ)
Test Conditions
ALL INPUT PULSES
90%
10%
THÉ VENIN EQUIVALENT
R
TH
OUTPUT
3.0V
1103
1554
645
1.75
Conditions
L (Auto-E)
LL (Ind'l/Auto-A)
V
> 1.5 V
DR
> 100 µs.
CC(min.)
CY62147DV30
Max.
Unit
10
pF
10
pF
VFBGA
TSOP II
°C/W
72
75.13
°C/W
8.86
8.95
90%
10%
Fall Time = 1 V/ns
V
Unit
Ω
Ω
Ω
V
[5]
Min.
Typ.
Max.
1.5
15
6
0
t
RC
V
CC(min)
t
R
Page 4 of 12
Unit
Unit
V
µA
ns
ns
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