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Switching Characteristics

[9]
Over the Operating Range
Parameter
Read Cycle
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE
LOW and CE
ACE
1
t
OE LOW to Data Valid
DOE
t
OE LOW to Low Z
LZOE
t
OE HIGH to High Z
HZOE
t
CE
LOW and CE
LZCE
1
t
CE
HIGH or CE
HZCE
1
t
CE
LOW and CE
PU
1
t
CE
HIGH or CE
PD
1
[12]
Write Cycle
t
Write Cycle Time
WC
t
CE
LOW and CE
SCE
1
t
Address Setup to Write End
AW
t
Address Hold from Write End
HA
t
Address Setup to Write Start
SA
t
WE Pulse Width
PWE
t
Data Setup to Write End
SD
t
Data Hold from Write End
HD
t
WE LOW to High Z
HZWE
t
WE HIGH to Low Z
LZWE
Notes
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of V
levels of 0 to V
, and output loading of the specified I
CC(typ)
10. At any given temperature and voltage condition, t
11. t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE
HZCE
HZWE
12. The internal write time of the memory is defined by the overlap of WE, CE
can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05684 Rev. *D
Description
HIGH to Data Valid
2
[10]
[10, 11]
[10]
HIGH to Low Z
2
[10, 11]
LOW to High Z
2
HIGH to Power Up
2
LOW to Power Down
2
HIGH to Write End
2
[10, 11]
[10]
/I
as shown in
"AC Test Loads and Waveforms"
OL
OH
is less than t
, t
HZCE
LZCE
HZOE
= V
1
IL
on page 4.
is less than t
, and t
is less than t
LZOE
HZWE
, and CE
= V
. All signals must be ACTIVE to initiate a write and any of these signals
2
IH
CY62158E MoBL
45 ns
Unit
Min
Max
45
ns
45
ns
10
ns
45
ns
22
ns
5
ns
18
ns
10
ns
18
ns
0
ns
45
ns
45
ns
35
ns
35
ns
0
ns
0
ns
35
ns
25
ns
0
ns
18
ns
10
ns
/2, input pulse
CC(typ)
for any given device.
LZWE
Page 5 of 10
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