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コンピュータ・ハードウェア Cypress Semiconductor CY7B9910のPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor CY7B9910 12 ページ。 Cypress low skew clock buffer specification sheet
ページを印刷するCapacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
C
Input Capacitance
IN
AC Test Loads and Waveforms
5V
R1=130
R1
R2=91
C
L
C
(Includes fixture and probe capacitance)
L
R2
7B9910–3
TTL AC Test Load (CY7B9910)
V
CC
R1=100
R2=100
R1
C
L
(Includes fixture and probe capacitance)
C
L
R2
7B9910–5
CMOS AC Test Load (CY7B9920)
Switching Characteristics
[11]
Over the Operating Range
Parameter
f
Operating Clock
NOM
Frequency in MHz
t
REF Pulse Width HIGH
RPWH
t
REF Pulse Width LOW
RPWL
t
Zero Output Skew (All Outputs)
SKEW
t
Device-to-Device Skew
DEV
t
Propagation Delay, REF Rise to FB Rise
PD
t
Output Duty Cycle Variation
ODCV
t
Output Rise Time
ORISE
t
Output Fall Time
OFALL
t
PLL Lock Time
LOCK
t
Cycle-to-Cycle Output Jitter Peak to Peak
JR
Document Number: 38-07135 Rev. *B
°
T
= 25
C, f = 1 MHz, V
A
= 50 pF (C
= 30pF for –5 and – 2 devices)
L
= 50 pF (C
=30 pF for –5 and – 2devices)
L
Description
[1, 2]
FS = LOW
[1, 2]
FS = MID
[1, 2, 3]
FS = HIGH
[13, 14]
[14, 15]
[16]
[17, 18]
[17, 18]
[19]
RMS
Test Conditions
= 5.0V
CC
2.0V
V
=1.5V
th
0.8V
0.0V
≤1ns
TTL Input Test Waveform (Cy7B9910)
80%
V
= V
/2
th
CC
20%
0.0V
≤ 3ns
CMOS Input Test Waveform (CY7B9920)
[8]
CY7B9910–2
Min
Typ
Max
15
30
25
50
40
80
5.0
5.0
0.1
0.25
0.75
–0.25
0.0
+0.25
–0.65
0.0
+0.65
0.15
1.0
1.2
0.15
1.0
1.2
0.5
200
25
CY7B9910
CY7B9920
Max
Unit
10
pF
3.0V
2.0V
V
=1.5V
th
0.8V
≤1ns
7B9910–4
V
CC
80%
V
= V
/2
th
CC
20%
≤ 3ns
7B9910–6
[8]
CY7B9920–2
Min
Typ
Max
15
30
MHz
25
50
[12]
40
80
5.0
ns
5.0
ns
0.1
0.25
ns
0.75
ns
–0.25
0.0
+0.25
ns
–0.65
0.0
+0.65
ns
0.5
2.0
2.5
ns
0.5
2.0
2.5
ns
0.5
ms
200
ps
25
ps
Page 5 of 11
Unit
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