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コンピュータ・ハードウェア Cypress Semiconductor CY7C0251AVのPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor CY7C0251AV 20 ページ。 3.3v 4k/8k/16k x 16/18 dual-port static ram

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Switching Characteristics
Over the Operating Range (continued)
Parameter
t
Write Pulse Width
PWE
t
Data Setup to Write End
SD
t
Data Hold From Write End
HD
[23, 24]
t
R/W LOW to High Z
HZWE
[23, 24]
t
R/W HIGH to Low Z
LZWE
[25]
t
Write Pulse to Data Delay
WDD
[25]
t
Write Data Valid to Read Data Valid
DDD
[26]
Busy Timing
t
BUSY LOW from Address Match
BLA
t
BUSY HIGH from Address Mismatch
BHA
t
BUSY LOW from CE LOW
BLC
t
BUSY HIGH from CE HIGH
BHC
t
Port Setup for Priority
PS
t
R/W HIGH after BUSY (Slave)
WB
t
R/W HIGH after BUSY HIGH (Slave)
WH
[27]
t
BUSY HIGH to Data Valid
BDD
[26]
Interrupt Timing
t
INT Set Time
INS
t
INT Reset Time
INR
Semaphore Timing
t
SEM Flag Update Pulse (OE or SEM)
SOP
t
SEM Flag Write to Read Time
SWRD
t
SEM Flag Contention Window
SPS
t
SEM Address Access Time
SAA

Data Retention Mode

The
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV are designed for battery backup.
Data retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within V
to V
– 0.2V.
CC
CC
2. CE must be kept between V
during the power up and power down transitions.
3. The RAM can begin operation >t
minimum operating voltage (3.0V).
Notes
25. For information on port to port delay through RAM cells from writing port to reading port, refer to
26. Test conditions used are Load 2.
27. t
is a calculated parameter and is the greater of t
BDD
28. CE = V
, V
= GND to V
, T
CC
in
CC
A
Document #: 38-06052 Rev. *J
[20]
Description
– 0.2V and 70 percent of V
CC
after V
reaches the
RC
CC
– t
(actual) or t
WDD
PWE
= 25°C. This parameter is guaranteed but not tested.
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
Min
15
15
0
3
5
0
15
10
5
5
Timing
and
Data Retention Mode
V
3.0V
CC
CE
CC
Parameter
ICC
at VCC
DR1
Figure
12.
– t
(actual).
DDD
SD
-25
Max
Min
Max
20
15
0
12
15
0
45
50
30
35
20
20
20
20
20
20
17
17
5
0
17
20
25
20
20
20
20
12
5
5
20
25
3.0V
> 2.0V
V
CC
t
RC
V
to V
– 0.2V
CC
CC
V
IH
[28]
Test Conditions
Max
= 2V
50
DR
Page 10 of 19
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
μA
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