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コンピュータ・ハードウェア Cypress Semiconductor CY7C1302DV25のPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor CY7C1302DV25 19 ページ。 Cypress 9-mbit burst of two pipelined srams with qdrtm architecture specification sheet
ページを印刷するSwitching Characteristics
Cypress
Consortium
Parameter
Parameter
Output Times
t
t
CO
CHQV
t
t
DOH
CHQX
t
t
CHZ
CHZ
t
t
CLZ
CLZ
Notes:
23. t
, t
, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ
CLZ
24. At any given voltage and temperature t
Document #: 38-05625 Rev. *A
Over the Operating Range (continued)
Description
C/C Clock Rise (or K/K in single clock mode) to Data Valid
Data Output Hold after Output C/C Clock Rise (Active to Active)
Clock (C and C) Rise to High-Z (Active to High-Z)
Clock (C and C) Rise to Low-Z
is less than t
and, t
less than t
CHZ
CLZ
CHZ
[21]
[23, 24]
[23, 24]
.
CO
CY7C1302DV25
167 MHz
Min.
Max.
Unit
2.5
ns
1.2
ns
2.5
ns
1.2
ns
Page 15 of 18
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