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コンピュータ・ハードウェア Cypress Semiconductor CY7C1306BV25のPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor CY7C1306BV25 20 ページ。 Cypress 18-mbit burst of 2 pipelined sram with qdr architecture specification sheet
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[23]
Capacitance
Parameter
Description
C
Input Capacitance
IN
C
Clock Input Capacitance
CLK
C
Output Capacitance
O
AC Test Loads and Waveforms
0.75V
V
REF
OUTPUT
Z
= 50Ω
0
Device
Under
Test
ZQ
RQ =
250Ω
(a)
Switching Characteristics
Cypress
Consortium
Parameter
Parameter
[22]
t
V
Power
Cycle Time
t
t
K Clock and C Clock Cycle Time
CYC
KHKH
t
t
Input Clock (K/K and C/C) HIGH
KH
KHKL
t
t
Input Clock (K/K and C/C) LOW
KL
KLKH
t
t
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise
KHKH
KHKH
(rising edge to rising edge)
t
t
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
KHCH
KHCH
Set-up Times
t
t
Address Set-up to Clock (K and K) Rise
SA
SA
t
t
Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS
SC
SC
t
t
D
SD
SD
Hold Times
t
t
Address Hold after Clock (K and K) Rise
HA
HA
t
t
Control Signals Hold after Clock (K and K) Rise (RPS, WPS, BWS
HC
HC
t
t
D
HD
HD
Output Times
t
t
C/C Clock Rise (or K/K in single clock mode) to Data Valid
CO
CHQV
t
t
Data Output Hold after Output C/C Clock Rise (Active to Active)
DOH
CHQX
t
t
Clock (C and C) rise to High-Z (Active to High-Z)
CHZ
CHZ
t
t
Clock (C and C) rise to Low-Z
CLZ
CLZ
Notes:
21. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250
pulse levels of 0.25V to 1.25V, and output loading of the specified I
22. This part has a voltage regulator that steps down the voltage internally; t
or write operation can be initiated.
23. At any given voltage and temperature t
Document #: 38-05627 Rev. *A
Test Conditions
T
= 25°C, f = 1 MHz,
A
V
= 2.5V.
DD
V
= 1.5V
DDQ
V
REF
OUTPUT
R
= 50Ω
L
Device
Under
V
= 0.75V
ZQ
REF
Test
Over the Operating Range
(typical) to the First Access Read or Write
CC
Set-up to Clock (K and K) Rise
[x:0]
Hold after Clock (K and K) Rise
[x:0]
[23, 24]
/I
OL
is less than t
and, t
less than t
CHZ
CLZ
CHZ
V
= 0.75V
REF
0.75V
R = 50Ω
0.25V
5 pF
RQ =
250Ω
(b)
[21]
Description
, BWS
0
[23, 24]
and load capacitance shown in (a) of AC test loads.
OH
is the time power needs to be supplied above V
Power
.
CO
CY7C1303BV25
CY7C1306BV25
Max.
Unit
5
pF
6
pF
7
pF
[21]
ALL INPUT PULSES
1.25V
0.75V
Slew Rate = 2 V/ns
167 MHz
Min.
Max.
10
6.0
2.4
2.4
2.7
3.3
0.0
2.0
0.7
)
0.7
1
0.7
0.7
, BWS
)
0.7
0
1
0.7
2.5
1.2
2.5
1.2
Ω
, V
= 1.5V, input
DDQ
minimum initially before a read
DD
Page 16 of 19
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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