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コンピュータ・ハードウェア Cypress Semiconductor CY7C1324HのPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor CY7C1324H 16 ページ。 Cypress 2-mbit (128k x 18) flow-through sync sram specification sheet
ページを印刷するTiming Diagrams
(continued)
[15, 17, 18]
Read/Write Timing
CLK
t
CH
t ADS
t ADH
ADSP
ADSC
t AS
t AH
ADDRESS
A1
A2
BWE, BW
[A:B]
t CES
t CEH
CE
ADV
OE
High-Z
Data In (D)
Data Out (Q)
Q(A1)
Back-to-Back READs
Notes:
17. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
18. GW is HIGH.
Document #: 001-00208 Rev. *B
t CYC
t
CL
A3
t
t
WES
WEH
t DS
t DH
D(A3)
t
OEHZ
Q(A2)
Single WRITE
A4
t OELZ
t CDV
Q(A4)
Q(A4+1)
Q(A4+2)
BURST READ
DON'T CARE
UNDEFINED
CY7C1324H
A5
A6
D(A5)
D(A6)
Q(A4+3)
Back-to-Back
WRITEs
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