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コンピュータ・ハードウェア Cypress Semiconductor CY7C1324HのPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor CY7C1324H 16 ページ。 Cypress 2-mbit (128k x 18) flow-through sync sram specification sheet

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Switching Characteristics

Parameter
t
V
(Typical) to the First Access
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid after CLK Rise
CDV
t
Data Output Hold after CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
OE LOW to Output Valid
t
OEV
OE LOW to Output Low-Z
t
OELZ
OE HIGH to Output High-Z
t
OEHZ
Set-up Times
t
Address Set-up before CLK Rise
AS
ADSP, ADSC Set-up before CLK Rise
t
ADS
ADV Set-up before CLK Rise
t
ADVS
t
GW, BWE, BW
WES
t
Data Input Set-up before CLK Rise
DS
t
Chip Enable Set-up
CES
Hold Times
t
Address Hold after CLK Rise
AH
t
ADSP, ADSC Hold after CLK Rise
ADH
t
GW, BWE, BW
WEH
t
ADV Hold after CLK Rise
ADVH
t
Data Input Hold after CLK Rise
DH
t
Chip Enable Hold after CLK Rise
CEH
Notes:
9. Timing reference level is 1.5V when V
10. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
11. This part has a voltage regulator internally; t
can be initiated.
12. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
13. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
Document #: 001-00208 Rev. *B
Over the Operating Range
Description
[11]
[12, 13, 14]
[12, 13, 14]
[12, 13, 14]
[12, 13, 14]
Set-up before CLK Rise
[A:B]
Hold after CLK Rise
[A:B]
= 3.3V and 1.25V when V
DDQ
DDQ
is the time that the power needs to be supplied above V
POWER
is less than t
and t
OEHZ
OELZ
CHZ
[9, 10]
Min.
1
7.5
2.5
2.5
2.0
0
0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
= 2.5V
(minimum) initially before a Read or Write operation
DD
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
CY7C1324H
-133
Max.
Unit
ms
ns
ns
ns
6.5
ns
ns
ns
3.5
ns
3.5
ns
ns
3.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 9 of 15
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