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コンピュータ・ハードウェア Cypress Semiconductor CY7C1333HのPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor CY7C1333H 13 ページ。 Cypress 2-mbit (64k x 32) flow-through sram with nobl architecture specification sheet

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[11]
Capacitance
Parameter
C
Input Capacitance
IN
C
Clock Input Capacitance
CLOCK
C
I/O Capacitance
I/O
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z
= 50Ω
0
V
= 1.5V
L
(a)
Switching Characteristics
Parameter
t
V
(Typical) to the First Access
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid after CLK Rise
CDV
t
Data Output Hold after CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
t
OE LOW to Output Valid
OEV
t
OE LOW to Output Low-Z
OELZ
t
OE HIGH to Output High-Z
OEHZ
Set-up Times
t
Address Set-up before CLK Rise
AS
t
ADV/LD Set-up before CLK Rise
ALS
t
WE, BW
WES
t
CEN Set-up before CLK Rise
CENS
t
Data Input Set-up before CLK Rise
DS
t
Chip Enable Set-Up before CLK Rise
CES
Notes:
12. Timing reference level is 1.5V when V
13. Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
14. This part has a voltage regulator internally; t
can be initiated.
15. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
16. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions
17. This parameter is sampled and not 100% tested.
Document #: 001-00209 Rev. **
PRELIMINARY
Description
T
V
V
3.3V
OUTPUT
R
= 50Ω
L
5 pF
INCLUDING
JIG AND
SCOPE
Over the Operating Range
Description
[14]
[15, 16, 17]
15, 16, 17]
[15, 16, 17]
[15, 16, 17]
Set-up before CLK Rise
[A:D]
=3.3V
DDQ
is the time that the power needs to be supplied above V
POWER
is less than t
and t
OEHZ
OELZ
CHZ
Test Conditions
100 TQFP Package
= 25°C, f = 1 MHz,
A
= 3.3V
DD
=3.3V
DDQ
R = 317Ω
V
DDQ
10%
GND
R = 351Ω
≤ 1 ns
(b)
[12, 13]
133 MHz
Min.
1
7.5
2.5
2.5
2.0
0
0
1.5
1.5
1.5
1.5
1.5
1.5
minimum initially before a Read or Write operation
DD
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
CY7C1333H
Unit
5
pF
5
pF
5
pF
ALL INPUT PULSES
90%
90%
10%
≤ 1 ns
(c)
100 MHz
Max.
Min.
Max.
Unit
1
ms
10
ns
4.0
ns
4.0
ns
6.5
8.0
ns
2.0
ns
0
ns
3.5
3.5
ns
3.5
3.5
ns
0
ns
3.5
3.5
ns
2.0
ns
2.0
ns
2.0
ns
2.0
ns
2.0
ns
2.0
ns
Page 8 of 12
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