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Timing Diagrams

(continued)

[21, 22]

ZZ Mode Timing

CLK

SUPPLY

ALL INPUTS

(except ZZ)

Outputs (Q)

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz)

Ordering Code

133

CY7C1365C-133AXC

CY7C1365C-133AJXC

CY7C1365C-133AXI

CY7C1365C-133AJXI

100

CY7C1365C-100AXC

CY7C1365C-100AJXC

CY7C1365C-100AXI

CY7C1365C-100AJXI

Notes:

21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

22. DQs are in High-Z when exiting ZZ sleep mode.

Document #: 38-05690 Rev. *E

t ZZ

t ZZI

DDZZ

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for actual products offered.

Package

Diagram

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(3 Chip Enable)