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ページを印刷するHS/FS Interface Timing - 30 MHz
CLK
Control_In
DataIn
Control_Out
DataOut
Table 4. 30 MHz Timing Interface Timing Constraints Parameters
Parameter
T
Minimum setup time for TXValid
CSU_MIN
T
Minimum hold time for TXValid
CH_MIN
T
Minimum setup time for Data (Transmit direction)
DSU_MIN
T
Minimum hold time for Data (Transmit direction)
DH_MIN
T
Clock to Control Out time for TXReady, RXValid,
CCO
RXActive and RXError
T
Clock to Data out time (Receive direction)
CDO
T
Minimum setup time for ValidH (transmit Direction)
VSU_MIN
T
Minimum hold time for ValidH (Transmit direction)
VH_MIN
T
Clock to ValidH out time (Receive direction)
CVO
Suspend
Tri-state
Output / IO
Table 5. Tri-state Mode Timing Constraints Parameters
Parameter
T
Minimum setup time for Tri-state
tssu
T
Propagation Delay for Tri-State mode
tspd
Document #: 38-08052 Rev. *G
Figure 4. 30 MHz Timing Interface Timing Constraints
TCH_MIN
TCSU_MIN
TDH_MIN
TDSU_MIN
TVH_MIN
TVSU_MIN
Description
Figure 5. Tri-state Mode Timing Constraints
Ttssu Ttspd
XXXX
Description
TCDO
TCCO
TCVO
Min
Typ
Max
16
1
16
1
1
20
1
20
16
1
1
20
Ttspd
Hi-Z
Min
Typ
Max
0
50
CY7C68000A
Unit
Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Notes
ns
ns
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