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コンピュータ・ハードウェア Cypress Semiconductor NoBL CY7C1352GのPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor NoBL CY7C1352G 13 ページ。 4-mbit (256k x 18) pipelined sram with nobl architecture

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Interleaved Burst Address Table
(MODE = Floating or V
First
Second
Address
Address
A1, A0
A1, A0
00
01
01
00
10
11
11
10
ZZ Mode Electrical Characteristics
Parameter
I
Snooze mode standby current
DDZZ
t
Device operation to ZZ
ZZS
t
ZZ recovery time
ZZREC
t
ZZ active to snooze current
ZZI
t
ZZ inactive to exit snooze current
RZZI
[2, 3, 4, 5, 6, 7, 8]
Truth Table
Operation
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/WRITE ABORT (Begin Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)

SNOOZE MODE

Truth Table for Read/Write
Read
Write − No bytes written
Write Byte A − (DQ
and DQP
A
Write Byte B − (DQ
and DQP
B
Write All Bytes
Notes:
2. X="Don't Care." H = Logic HIGH, L = Logic LOW. CE stands for ALL Chip Enables active. BW X = L signifies at least one Byte Write Select is active, BW X = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
3. Write is defined by BW
, and WE. See Write Cycle Descriptions table.
[A:B]
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
OE is inactive or when the device is deselected, and DQs and DQP
Document #: 38-05514 Rev. *D
)
DD
Third
Fourth
Address
Address
A1, A0
A1, A0
10
11
11
10
00
01
01
00
Description
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Address
Used
CE
None
H
None
X
External
L
Next
X
External
L
Next
X
External
L
Next
X
None
L
Next
X
Current
X
None
X
[2, 3]
Function
)
A
)
B
[A:B]
Linear Burst Address Table (MODE = GND)
First
Second
Address
Address
A1, A0
A1, A0
00
01
01
10
10
11
11
00
Test Conditions
− 0.2V
DD
− 0.2V
DD
ZZ
ADV/LD
WE
BW
x
L
L
X
X
L
H
X
X
L
L
H
X
L
H
X
X
L
L
H
X
L
H
X
X
L
L
L
L
L
H
X
L
L
L
L
H
L
H
X
H
L
X
X
X
H
X
X
X
WE
H
L
L
L
L
= data when OE is active.
CY7C1352G
Third
Fourth
Address
Address
A1, A0
A1, A0
10
11
11
00
00
01
01
10
Min.
Max.
40
2t
CYC
2t
CYC
2t
CYC
0
OE
CEN
CLK
DQ
X
L
L-H
Tri-State
X
L
L-H
Tri-State
L
L
L-H
Data Out (Q)
L
L
L-H
Data Out (Q)
H
L
L-H
Tri-State
H
L
L-H
Tri-State
X
L
L-H
Data In (D)
X
L
L-H
Data In (D)
X
L
L-H
Tri-State
X
L
L-H
Tri-State
X
H
L-H
–
X
X
X
Tri-State
BW
BW
B
A
X
X
H
H
H
L
L
H
L
L
= tri-state when
[A:B]
Page 5 of 12
Unit
mA
ns
ns
ns
ns
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