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計測機器 EG&G ORTEC 553のPDF 操作・サービスマニュアルをオンラインで閲覧またはダウンロードできます。EG&G ORTEC 553 16 ページ。 Timing single-channel analyzer

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CIRCUIT DESCRIPTION

5.1.

GENERAL

Refer to schematic diagram 553-0201-S1 included at the

back of the manual.

Figure 5.1 is a simplified block diagram of the 553 Timing

SCA. It shows that each input pulse is furnished to three

internal discriminators and also through an attenuate

and peak stretch circuit. The three discriminators are UL

(upper level), LL (lower level), and CP (constant frac

tion). Each discriminator independently triggers a re

sponse when the amplitude of its noninverted input

exceeds the amplitude of its inverted input. The response

of the UL and LL discriminators is latched until an

internal reset occurs. The CP discriminator is reset again

when the input conditions are reversed.

Reference levels for the UL and LL discriminators are set

independently for either Integral or Normal mode opera

tion. For Window operation, the threshold for the UL

discriminator is based on the LL setting instead of

ground.

The CP discriminator is triggered at the onset of each

input pulse, whether its amplitude is sufficient to trigger

either of the other two discriminators or not. Then the CP

discriminator is reset when the amplitude of the input

pulse decays through its 50% level because the attenuate

and peak stretch circuit has generated and maintained

this 50% level by that time and furnished it as the

discriminator reference level.

The SCA gate is triggered when the CP discriminator is

reset if, at that time, the LL discriminator has been

triggered and the UL discriminator either has not been

triggered (for differential operation) or is ignored (for

integral operation). Thus the gate responds to both

logical conditions and input-pulse time significance.

If the SCA gate responds, it strobes a delay circuit that

then generates the SCA outputs at the end of the delay

interval.

5.2.

INTEGRATED CIRCUITS

The nomenclature used to identify integrated circuit

packages in this manual is defined below for the example

IC5(4)

where

IC = integrated circuit,

5 = reference designation,

(4) = pin number.

Any portion of an IC package can be designated by its

output pin number: in this example, the portion of IC5

that includes pin 4 as an output is identified uniquely.

5.3.

LOWER LEVEL BIAS

The threshold for the lower level discriminator is ad

justed with the front panel Lower Level control, R43, or is

OUTPUT

Int

GENERATOR

UL DISC

Nor/Win

DC In

Int/Nor

LL DISC

DELAY

OUTPUT

GENERATOR

CF DISC

ATTENUATE

and

PEAK STRETCH

CURRENT

SWITCH

UL Out

-0

Pos Out

-0

Neg Out

Fig. 5.1. Simplified Block Diagram of tfie 553 Timing SCA.