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マルチプレクサ EG&G ORTEC 476のPDF 取扱説明書をオンラインで閲覧またはダウンロードできます。EG&G ORTEC 476 14 ページ。 Multiplexer/routar

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The largest jumper block permits the four available rout

ing output bits to be connected across to any four adja-

cent address bits within the limits of FEDS through FED 15.

When the unit is shipped from the factory, these jumpers

are set to select FED12 through FED15; software in the

DAAS may be used to translate these selections to the

four most significant bits in whatever memory size is

included. If desired, the four jumpers can be moved to

any four adjacent output lines within the range that is

identified.

3.6. INTERNAL TIME CONSTANT SELECTIONS

Each channel in the 476 has an input circuit that includes

a group of four time constant selection switches. These

are miniature slide switches mounted across the bottom

of the printed circuit. The switch assembly toward the

rear panel is associated with channel 0 (the Linear Input

1 connector), and the assembly toward the front panel is

used for the highest numbered channel.

The four switches in each assembly are numbered (1, 2,

3, and 4). Only one of these four switches is to be set at

the On position. Use the switch that is appropriate for the

shaping time of the input pulses. Use switch 1 if the input

is shaped with a l-^s time constant or if it is stretched for

at least 2 /js. Use switch 2 if the input has 2-fiS shaping.

Use switch 3 for 3 nS. Use switch 4 for 6-ns shaping.

Note that the shaping time constant selection for each

channel is completely independent from all other chan

nels.

OPERATION

4.1. THRESHOLD ADJUSTMENT

The Threshold control at the upper left on the front panel

is used to set the discrimination level just above the sys

tem noise, and this is common to all input channels. The

range for this control is 0 to 100 mV, which should be

adequate for any normal application.

4.2. FINE GAIN ADJUSTMENTS

Each channel in the 476 includes a Fine Gain screwdriver

control on the front panel. This control is used, when

required, to equalize small differences in the linear gain

between channels. The range of each control is limited to

±0.34%. Larger gain changes should be controlled at the

input amplifier in the system; this is for trim purposes

only.

The intended gain factor for each signal that passes

through the linear portion of the 476 is unity. The effective

gain through each channel can be measured by setting

the front panel toggle switch at Channel Select and then

turning the Channel Selector switch to each channel that

is to be examined. A dynamic check, using a radioactive

source to affect each related detector, is recommended.

When the testing has been accomplished, return the

toggle switch to Normal Multiplex (the Channel Selector

is ineffective for this toggle switch setting).

4.3. OPERATING PROCEDURES

After the 476 has been installed according to the informa

tion in Section 3, and its threshold and gain adjustments

have been made, no further operating controls are re

quired. Each input pulse from any of its sources will

trigger a logic response that will generate a routing output

identification; the response to one input will also inhibit

any input pulse through an alternate channel until the

first pulse has been transferred to the ADC. The Busy

indicator on the 476 front panel provides a visual indi

cation that input signal amplitudes are exceeding the

threshold; it can be used as an aid when adjusting the

Threshold control. The internally generated routing

signal is also used to gate the linear signal through to

the Linear Out connector on the rear panel.

5. CIRCUIT DESCRIPTION

5.1.

GENERAL

The schematic for the EG&G ORTEC 476 Multiplexer/

Router is 476-0201-S1, included at the back of this

manual. All the circuits are included on the single printed

circuit board and on the front and rear panels. The follow

ing parts are included in the circuits:

1. Sixteen Linear Input circuits. Each input signal is

furnished through a Fine Gain adjustment and into an

analog multiplexer. The logic circuit selects one of the 16

inputs according to a 4-line binary code (the internally

generated routing signal).

2. Each input signal is also furnished into a logical gate

that identifies the channel into which the signal is re

ceived and permits gating for that signal together with

lockout of any subsequent input signal(s) until the first

has been transferred.