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Notice that, as supplied, C6 is shorted with a jumper wire

and the output is dc-coupled. There will be a small dc offset

voltage that is dependent on the saturation properties of the

gate transistors that will have to be considered when going

into an ADC or other dc-coupled units. Capacitor C6 is

provided to allow ac-coupling in these cases, but polarity of

the offset must be determined to properly connect the solid

tantalum electrolytic capacitor, C6.

5. CIRCUIT DESCRIPTION

5.1. LINEAR GATE - ETCHED BOARD 426-0201

The input to the Linear Gate can be either ac- or dc-coupled.

Refer to Drawings 426-0000-S2 and 426-0200-82. The ac-

coupled signal is fed in on the etched board and then into

the baseline recovery network consisting of diodes D1

through D4 and resistors R1 and R40. The dc restoration

network works as follows. With the application of a positive

input signal it is coupled through capacitor C1 to the junc

tion of D2 and R1. As the junction of D2-R1 increases in

the positive direction, the current through D1 increases

while the current through D2 decreases due to the current

flow out of capacitor C1 through R1. The current flow out

of C1 and through R1 Is the current necessary to maintain

the amplitude of the input voltage at the junction of D2 and

R1 . With the removal of the input pulse, the quiescent cur

rent flow through D1 is available to recharge capacitor C1

back to its steady-state value, since the current through D1

can be reduced to zero and the current through D2 can

increase in magnitude to a value of twice that through D1.

Therefore the potential at the junction of D2 and R1 will be

restored to its steady-state value in a period of time

approximately equal to the pulse width of the incoming

pulse.

The Linear Gate will gate through positive signals or the

positive part of bipolar signals. The input signals are coupled

through emitter-follower Q1 to the collector of Q2, the

series section of a series-shunt linear gate. The positive part

of the input signal back-biases diode D6, while the negative

parts of bipolar signals are blocked by D5. In the steady-

state condition Q2 is normally off, since the current switch,

Q4 and Q5, is requiring a current through R9 of approxi

mately 4 mA. Q4 of the current switch is normally on, and

the current required in the emitter circuit of the current

switch is drawn from diode D7 and resistor R5. With the

heavy conduction of Q4, the base current for Q2 is zero;

therefore the series resistance of the collector to the emitter

of Q2 is very high. Conversely, transistor Q3 has a constant-

current base drive through R6 of approximately 1 mA and

diode D8 is back-biased, causing shunt transistor Q4 to be

heavily saturated.

With the application of a positive signal to the collector of

Q2 and with the absence of a signal to the current switch.

transistors Q4 and Q5, the series-shunt gate is closed for in

put signals to C1. The Linear Gate is opened by the ap

plication of a positive signal to the base of Q5, which causes

the current switch to switch its emitter current from Q4 to

Q5. When Q5 conducts the emitter current of the current

switch, the base drive to Q2 is available via R5, and con

currently, base current for Q3 becomes negligible since the

collector of Q5 requires approximately 4 mA. With the cur

rent switch conducting current in Q5, it is seen that Q2, the

series element, is in heavy saturation, with the base drive

current supplied from R5 flowing into the base through the

emitter and back through diode D11 to the emitter-follovyer,

Ql. Also, Q3, the shunt element in the linear gate, is now

back-biased and presents a high shunt impedance to signals

flowing through the series element, Q2.

With the series-shunt Linear Gate in the open position, i.e.,

Q2 saturated and Q4 back-biased, the output signals of

emitter-follower Ql are presented to emitter-follower 06

and then to the cascode emitter-follower consisting of 07

and 08. The output of the cascode emitter-follower is

taken from the emitter of 07 through C6 to the output of

the Linear Gate, CN2.

The current switch 04 and 05 is controlled by the enable

circuitry, consisting of transistors 09 through 013. With the

application of a positive Enable signal at CN3 greater than

2 V the input trigger circuit generates a standardized out

put pulse that is fed to the "gate width" trigger pair, 012

and 013. 09 and 010 constitute a Schmitt trigger circuit

which wi l l change from its quiescent current-carrying state

when the input signal at the base of 09 exceeds the base

voltage of O10. In the quiescent state 09 is Off and O10 is

On and conducting approximately 4 mA through R27. This

trigger circuit is independent of the input pulse shape since

it is dc-coupled. When the quiescent current .is transferred

from O10 to 09, a positive voltage spike is generated at the

collector of O10 due to LI and R24. This signal causes 011,

which is normally off, to conduct current through R31,

which generates a negative voltage spike at the collector of

011. This signal is coupled to the base of 013 through C8.

013 is normally on and 012 is normally off due to the for

ward bias on the base of 013 from D9. With the negative