Bose Lifestyle 28 문제 해결 매뉴얼 - 페이지 27
{카테고리_이름} Bose Lifestyle 28에 대한 문제 해결 매뉴얼을 온라인으로 검색하거나 PDF를 다운로드하세요. Bose Lifestyle 28 32 페이지. Dvd home entertainment systems
Bose Lifestyle 28에 대해서도 마찬가지입니다: 설치 매뉴얼 (32 페이지), 운영 매뉴얼 (44 페이지), 소유자 매뉴얼 (22 페이지), 운영 매뉴얼 (46 페이지), 운영 매뉴얼 (44 페이지), 운영 매뉴얼 (34 페이지)
페이지 인쇄
- 1. Table of Contents
- 2. Safety Information
- 3. Electrostatic Discharge Senstitive (ESDS) Device Handling
- 4. Specifications
- 5. Theory of Operation
- 6. Theory of Operation
- 7. Setting up a Computer to Issue TAP Commands
- 8. Placing the Bass Module into TAP Mode
- 9. Equalizer Programming Method
- 10. Scope Photos
- 11. Scope Photos
- 12. Integrated Circuit Diagrams
- 13. Troubleshooting Guide
Pin
Type
ADDR 23-0
I/O/T
External Bus Address. The ADSP-21065L outputs addresses for external
memory and peripherals on these pins. In a multiprocessor system the bus
master outputs addresses for read/writes of the internal memory or IOP
registers of other ADSP-21065L. The ADSP-21065L inputs addresses when
a host processor or multiprocessing bus master is reading or writing its internal
memory or IOP registers.
DATA 31-0
I/O/T
External Bus Data. The ADSP-21065L inputs and outputs data and instructions
on these pins. The external data bus transfers 32-bit single-precision floating-point
data and 32-bit fixed-point data over 31-0. 16-bit short word data is transferred
over Bits 15-0 of the bus. Pull-up resistors on unused DATA pins are not
necessary.
Memory Select Lines. These lines are asserted (low) as chip selects for the
___
O/T
MS
corresponding banks of external memory. Internal ADDR25-24 are decoded into
3-0
MS 3-0 . The MS 3-0 lines are decoded memory address lines that change at the
same time as the other address lines. When no external memory access is
occurring, the MS 3-0 lines are inactive. They are active, however, when a
conditional memory access instruction is executed, whether or not the condition is
true. Additionally an MS O which is mapped to SDRAM may be asserted even
when no SDRAM access is active. In a multiprocessor system, the MS 3-0 lines
are output by the bus master.
___
I/O/T
Memory Read Strobe. This pin is asserted (low) when the ADSP-21065L's reads
RD
from external memory devices or from the internal IOP register of another ADSP-
21065L. External devices (including other ADSP 21065L's) must assert RD to read
from the ADSP-21065L's internal IOP registers. In a multi-processor system RD is
output by the bus master and is input by all other ADSP-21065L.
___
I/O/T
Memory Write Strobe. This pin is asserted (low) when the ADSP-21065L
WR
writes to external memory devices or to the internal memory of other ADSP-
21065L's. External devices must assert WR to write to the ADSP-21065L's IOP
registers. In a multiprocessor system WR is output by the bus master and is input
by all other ADSP-21065L.
___
I/O/T
Synchronous Write Select. This signal is used to interface the ADSP-21065L to
SW
synchronous memory devices (including other ADSP-21065L). The ADSP-21065L
asserts SW (low) to provide an early indication of an impending write cycle, which
can be aborted if WR is not later asserted (e.g. in a conditional write instruction). In
a multiprocessor system, SW is output by the bus master and is input by all other
ADSP-21065L to determine if the rnultiprocessor memory access is a read or
write. SW is asserted at the same time as the address output.
ACK
I/O/S
Memory Acknowledge. External devices can deassert ACK (low) to add wait
states to an external memory access.. ACK is used by I/O devices, memory
controllers or other peripherals to hold off completion of an external memory
access. The ADSP-21065 deasserts ACK as an output to add wait states to a
synchronous access of its IOP registers. In a multiprocessor system, a slave
ADSP-21065 deasserts the bus master's ACK input to add wait state(s) to an
access of its IOP registers. The bus master has a keeper latch on its ACK pin that
maintains the input at the level it was last driven.
Suspend Bus Three-State. External devices can assert SBTS (low) to place
_____
I/S
SBTS
the external bus address, data, selects, and strobes, but not SDRAM pins in a high
impedance state for the following cycle. If the ADSP-21065L attempts to access
external memory while SBTS is asserted, the processor will halt and the memory
access will not be completed until SBTS is deasserted. SBTS should only be used
to recover from PAGE faults or host processor/ADSP-21065L deadlock.
___
I/A
Interrupt Request Lines. May be either edge-triggered or level-sensitive.
IRQ, 2-0
Integrated Circuit Diagrams
DSP ADSP21065LKS
part number 254191-001
27
PS18/28/35 Troubleshooting Guide
Function