Bose Lifestyle 48 문제 해결 매뉴얼 - 페이지 28
{카테고리_이름} Bose Lifestyle 48에 대한 문제 해결 매뉴얼을 온라인으로 검색하거나 PDF를 다운로드하세요. Bose Lifestyle 48 32 페이지. Personal music center ii - owner's guide
Bose Lifestyle 48에 대해서도 마찬가지입니다: 설치 매뉴얼 (42 페이지), 매뉴얼 (29 페이지), 설치 매뉴얼 (36 페이지), 소유자 매뉴얼 (25 페이지), 소유자 매뉴얼 (24 페이지), 소유자 매뉴얼 (13 페이지), 빠른 설정 매뉴얼 (3 페이지), 소유자 매뉴얼 (30 페이지)
페이지 인쇄
- 1. Table of Contents
- 2. Safety Information
- 3. Electrostatic Discharge Senstitive (ESDS) Device Handling
- 4. Specifications
- 5. Theory of Operation
- 6. Theory of Operation
- 7. Setting up a Computer to Issue TAP Commands
- 8. Placing the Bass Module into TAP Mode
- 9. Equalizer Programming Method
- 10. Scope Photos
- 11. Scope Photos
- 12. Integrated Circuit Diagrams
- 13. Troubleshooting Guide
Pin
Type
FLAG 11-0
I/O/A
Flag Pins. Each is configured via control bits as either an input or an output. As an
input, it can be tested as a condition. As an output, it can be used to signal
external peripherals.
____
I/A
Host Bus Request. Must be asserted by a host processor to request control
HBR
of the ADSP-21065L's external bus. When HBR is asserted in a multiprocessing
system, the ADSP-21065L that is bus master will relinquish the bus and assert
HBG. To relinquish the bus, the ADSP-21065L places the address, data, select,
and strobe lines in a high impedance state. HBR has priority over all ADSF-21065L
bus requests (BR 2-1 ) in a multiprocessing system.
____
I/0
Host Bus Grant. Acknowledges an HBRbus request, indicating that the host
HBG
processor may take control of the external bus. HBG is asserted by the ADSP-
21065L until HBR is released. In a Multiprocessing system, HBG is output by the
ADSP-21065L bus master.
___
I/A
Chip Select. Asserted by host processor to select the ADSP-21065L.
CS
REDY
O
Host Bus Acknowledge. The ADSP-21065L de-asserts REDY to add wait states
(O/D)
to an asynchronous access of its internal memory or IOP registers by a host. Open
drain output (O/D) by default can be programmed in ADREDY bit of SYSCON
register to be active drive (A/D). REDY will only be output if the CS and HBR
inputs are asserted.
______
I/A
DMA Request 1 (DMA Channel 9).
DMAR1
______
I/A
DMA Request 2 (DMA Channel 8).
DMAR2
DMA Grant 1 (DMA Channel 9).
______
O/T
DMAG1
DMA Grant 2 (DMA Channel 8).
______
O/T
DMAG2
_____
I/O/S
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21065Ls
BR
to arbitrate for bus master ship. An ADSP-21065L drives its own BRx line
2-1
(corresponding to the value of its ID 2-0 inputs) only and monitors all others. In a
uniprocessor system tie both BRx pin to V DD
ID 1-0
I
Multiprocessing ID. Determines which multiprocessing bus request (BR 1 -BR 2 )
is used by ADSP-21065L. ID = 01 corresponds to BR 1 , ID = 10 corresponds to
BR 2 , etc. ID = 00 in single-processor systems. These lines are a system
configuration selection which should be hardwired or changed only at reset.
Core Priority Access. Asserting its CPA pin allows the core processor of
____
I/O
CPA (O/D)
an ADSP-21065L bus slave to interrupt background DMA transfers and gain
access to the external bus. CPA is an open drain output that is connected to all
ADSP-21065Ls in the system. The CPA pin has an internal 5 k pull-up resistor. If
core access priority is not required in a system, the CPA pin should be left
unconnected.
DTxX
O
Data Transmit (Serial Ports 0, 1; channels A, B). Each DTxX pin has a 50k
internal pull-up resistor.
DRxX
I
Data Receive (Serial Ports 0, 1;channels A, B). Each DRxX pin has a 50 k
internal pull-up resistor.
TCLKx
I/O
Transmit Clock (Serial Porcs 0, 1). Each TCLKx pin has a 50 k internal pull-up
resistor.
RCLKx
I/O
Receive Clock (Serial Ports 0. 1). Each RCLKx pin has a 50 k . internal pull-up
resistor.
Transmit Frame Sync (Serial Ports 0, 1).
TFSx
I/O
RFSx
I/O
Receive Frame Sync (Serial Ports 0, 1).
Integrated Circuit Diagrams
DSP ADSP21065LKS
part number 254191-001
28
PS18/28/35 Troubleshooting Guide
Function