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INTERRUPTS

Chapter 2 Interrupt Types

2 Interrupt Types

THE BASIC FUNCTIONALITY OF INTERNAL INTERRUPTS

2.1 Available Exceptions / Interrupts / Traps

There are different types of Interrupts / exceptions / traps available.

2.1.1 Interrupts

2.1.1.1 Peripheral Interrupts

These kinds of Interrupts are generated by internal resources hence the may also referred to

as "external" since they originate outside the CPU. An Interrupt is generated if the

corresponding interrupt enable bit of the resource is set, the level of the vector is equal or

less than the global interrupt level, interrupts are globally enabled and an interrupt cause has

occurred. While execution of interrupt service routine (ISR), the System Stack Pointer is

enabled (CCR:S = 0). Interrupt level of peripheral interrupts is configured by ICRxx

(Interrupt Control Register).

It should be noted that one ICR configures (same) interrupt level for 2 peripheral resources.

For more details please refer the hardware manual.

2.1.1.2 Non-maskable Interrupts

Non-maskable interrupts (NMI) are interrupts that cannot be masked by software. This is

because it is not possible to write a value less than 16 using a software instruction.

NMI has a fixed interrupt level unlike peripheral interrupts. It is level 15. That means while

execution of NMI ISR, the interrupt level mask is configured to 15 (PS:ILM = 15). Hence all

the other interrupts (whose level is above 15) are suspended until NMI ISR execution has

finished. System Stack Pointer is enabled (CCR:S = 0). The ILM is restored at execution of

the RETI instruction.

2.1.2 Exceptions

Exceptions originate from within the instruction sequence. Exceptions are processed by first

saving the necessary information to resume the currently executing instruction, and then

starting the processing routine corresponding to the type of exception that has occurred.

2.1.2.1 Undefined Instruction

All codes that are not defined in the instruction map are handled as undefined instructions.

When an undefined instruction is executed, the ISR whose starting address is stored at

interrupt vector 14 is executed. While storing the CPU status, PC value saved in the stack is

the address at which the undefined instruction is stored. While execution of ISR, global

interrupt flag is cleared (CCR:I = 0), hence all the all peripheral interrupts are suspended

until undefined instruction ISR execution has finished. Undefined instruction ISR can not also

be interrupted by NMI and Traps. The System Stack Pointer is enabled (CCR:S = 0).

xx: 00 to 63

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MCU-AN-300055-E-V10