Fujitsu MB91460 SERIES 애플리케이션 노트 - 페이지 25

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3.2 DMAC Example with UART

The following example code shows how to configure the DMAC with the UART2. The DMAC

channel 0 is configured in the block transfer 2-cycle mode. Each block transfer would have

1-byte transferred. If the data is received on UART2 receive buffer RDR02 then the DMA

channel 0 transfers the same data to the UART2 transmit buffer TDR02. The transfer takes

places unless 50 receptions (since the DTC is set as 0x32) or if there is any error in the

reception. After DMAC interrupt gets generated and in the ISR DMAC interrupt flag is

cleared with 0xFF output to port 16.

Main.c

/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */

/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */

/* ELIGIBILITY FOR ANY PURPOSES.

/*---------------------------------------------------------------------------*/

void

Init_UART2(void)

{

BGR02 = 1666;

SCR02 = 0x17;

SSR02 = 0x02;

SMR02 = 0x0D;

PFR20_D0 = 1;

PFR20_D1 = 1;

EPFR20_D1 = 0;

}

void

Init_DMAC(void)

{

DMACR_DMAE = 1;

DMACA0_DENB = 0;

DMASA0 = (IO_LWORD)&RDR02;

DMADA0 = (IO_LWORD)&TDR02;

DMACA0_IS = 0x14;

DMACA0_EIS = 0x3

DMACB0_WS1 = 0; DMACB0_WS0 = 0;

DMACB0_EDIE = 1;

DMACB0_SASZ = 0;

DMACB0_DASZ = 0;

DMACB0_DTCR = 0;

DMACA0_BLK = 1;

DMACA0_DTC = 0x32;

DMACB0_MD1 = 0;

DMACB0_MD0 = 0;

DMACA0_DENB = 1;

}

DIRECT MEMORY ACCESS

Chapter 3 DMAC Examples

// 9600 baud at 16MHz CLKP1

// 8 bit, clear reception errors, Tx & Rx enabled

// LSB First, enable receive interrupts

// Mode 0, Reset Counter, Reset UART, SOT0 enabled

// enable UART

// Enable all DMAC channels

// Disable DMAC channel 0

// Source Start Address

// Destination Start Address

// UART02 receive

// Byte-width

// IRQ when transfer finished

// Source Address Same

// Destination Address Same

// Reload DTC Disable

// Block Value 1 byte

// DTC set as 50

// Block Mode

// Enable DMAC channel 0

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MCU-AN-300059-E-V11