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Debug Methodology and Failure Isolation

8.5.1

FRB3 – BSP Reset Failures

The first timer (FRB-3) starts counting down when the system comes out of hard reset. If the

Bootstrap Processor (BSP) successfully resets and begins executing, the BIOS disables the

FRB-3 timer in the BMC and the system continues executing POST. If the timer expires

because of the BSP failure to fetch or execute BIOS code, the BMC resets the system and

disables the failed processor. In this failing scenario, the BMC continues to change the BSP

until the BIOS successfully disables the FRB-3 timer. The BMC sounds beep codes on the

system speaker if it fails to find a good processor. It will continue to cycle until it finds a good

processor. The process of cycling through all the processors is repeated upon system reset or

power cycle. The duration of the FRB-3 timer is 6 minutes.

8.5.2

FRB2 – BSP POST Failures

The second timer (FRB-2) is set for approximately 6 minutes (pending tuning) by BIOS and is

designed to guarantee that the system completes POST. The FRB-2 timer is enabled just

before the FRB-3 timer is disabled to prevent any "unprotected" window of time. Before the

option ROMs are initialized, or if the password prompt is displayed, the BIOS disables the FRB-

2 timer. Finally, if the system is set to perform a processor late self-test, the FRB-2 timer will be

suspended.

If the system hangs during POST, before the BIOS disables the FRB-2 timer, the BMC

generates an asynchronous system reset (ASR). The BMC retains status bits that can be read

by BIOS later in the POST for the purpose of disabling the previously failing processor, logging

the appropriate event into the SEL, and displaying an appropriate error message to the user.

8.5.3

FRB1 – BSP Self-Test Failures

In addition to FRB-3 and FRB-2 timers, the BIOS provides FRB-1. Early in POST, the BIOS

checks the Built-in Self Test (BIST) results of the BSP. If the BSP fails BIST, the BIOS requests

the BMC to disable the BSP. The BMC disables the BSP, selects a new BSP and generates a

system reset. If there is no alternate processor available, the BMC beeps the system speaker

and enters into "final desperation mode", a scheme whereby the system will attempt to boot in

spite of failed processor(s).

The BIOS and BMC implement additional safeguards to detect and disable the application

processors (AP) in a multiprocessor system. If an AP fails to complete initialization within a

certain time, it is assumed to be nonfunctional. If the BIOS detects that an AP has failed BIST or

is nonfunctional, it requests the BMC to disable that processor. When the BMC disables the

processor and generates a system reset, the BIOS will not see the bad processor in the next

boot cycle. The failing AP is not listed in ACPI APIC tables, and is invisible to the OS.

8.5.4

FRB Debug Methodology

All the failures (FRB-3, FRB-2, FRB-1, and AP failures) including the failing processor are

recorded into the SEL. The FRB-3 failure is recorded automatically by the BMC, while the FRB-

2, FRB-1, and AP failures are logged to the SEL by the BIOS. In the case of an FRB-2 failure,

some systems will log additional information into the OEM data byte fields of the SEL entry.

This additional data indicates the last POST task that was executed before the FRB-2 timer

expired. This information may be useful for failure analysis.

Intel® Server Platform SR870BH2

Revision 1.1