Dell S3048-ON 문제 해결 매뉴얼 - 페이지 16

{카테고리_이름} Dell S3048-ON에 대한 문제 해결 매뉴얼을 온라인으로 검색하거나 PDF를 다운로드하세요. Dell S3048-ON 29 페이지. Enterprise switches

Dell S3048-ON 문제 해결 매뉴얼
read [b|h|w] address := read the specified physical address
write [b|h|w] address data [length] := write at the specified physical address
Example of the memtool Configuration File Output
//
Memory Configuration File
//
//
Example:
//
SystemRam:-:-:w:4:1:2800:0:0:1:-1:SPD:/dev/i2c-0:50:0,ff:
//
This describes the SystemRam which is dynamic in location and size.
words //
and incremented addresses of 4 bytes. It is ECC covered, and has a max chunk of
10KB max
//
cache and cacheline size (unused at this time) are 0.
on this
//
region, and the -1 denotes to run all tests, excluding dim cache memory test. The
Descriptive
//
device is a SPD on /dev/i2c-0 at address 0x50, and we read registers 0-255.
//
//
Note: a '-' address and size denotes a dynamic ram allocation
//
=======================Tests================================
//
-1
: all Tests Run
//
0h : No Address Test
//
1h : Address Read Test (Access)
//
2h : Address Read|Modify|Write|Verify
//
4h : Address walking 1's
//
8h : Address walking 0's
//
00h : No Data Test
//
10h : Data Read Test (Access)
//
20h : Data Read|Modify|Write|Verify
//
40h : Data walking 1's
//
80h : Data walking 0's
//
100h : Data walking 1's
//
200h : Data walking 0's
//
400h : patterns (00ff, ff00, 55aa, aa55)
//
800h : Cache (cacheKiller - Not Part of ALL Tests)
SystemRam:-:-:d:8:1:2800:-1:-1:1:-1:i2c:0x52,SPD,0,255

pltool

The programmable logic tool (pltool) verifies access to the complex programmable logic devices (CPLD) and field programmable gate
array (FPGA) and verifies versions.
The pltool generates its configuration file based on the platform database. The configuration file is generated with a specific version of
devices in order to detect manufacturing misleads. The database holds all the versions and is updated when new versions are released.
The configuration file displays in tree format. The base is the chip that can have multiple registers and may or may not have bit descriptions
and bit collection information. Each parameter in the tree is on an individual line separated by the "|" character.
Example of the pltool Output
Syntax: ./pltool <option>
read [b|h|w] device offset [length]
write [b|h|w] device offset data [length] := write at the specified register
The configuration file displays in tree format. The base is the chip that can have multiple registers and may or may not have bit descriptions
and bit collection information. Each parameter in the tree is on an individual line separated by the "|" character.
The following describes the C-row configuration file tree output.
16
ONIE diagnostics
-h := show this help
test := test using the test config file
list := list devices and registers
:= read the specified register
It is accessed by
The tests will be performed once