Chrontel CH7512B 디자인 매뉴얼 - 페이지 4

{카테고리_이름} Chrontel CH7512B에 대한 디자인 매뉴얼을 온라인으로 검색하거나 PDF를 다운로드하세요. Chrontel CH7512B 16 페이지. Edp/dp receiver

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CHRONTEL

The REFCK is another optional pin as the reference input clock for the CH7511B/7512B. A 27MHz (3.3V) clock

may be injected at this pin as shown in Figure 3. For PCB design, the capacitor must be placed as close as possible to

the REFCK pin, with traces connected from point to point, overlaying the ground plane.

Note: The resetb is 1.8V level.

It need 10Kohm resister to 1.8V

and 0.1uf capacitor to GND.

So if the system reset signal is 3.3V,

the level shift circuit is necessary.

CH 7511B

NOTE: CH7 511B su pports tw o

kin ds o f clo ck in put w ays

Op tion1 : us e 27 MHz crys tal w ith 2 2pf

ca pacitors

Op tion 2: in ject clock 27MHz (3.3V) in

REFCK pin (Pin 9)

Cu stom er m ust choo se o ne o ptio n

for CH7 511 B clo ck

2.4

Serial Port Control Pins

• SPC0 and SPD0

SPD0 and SPC0 function as a serial interface where SPD0 is the bi-directional data and SPC0 is an input-only serial

clock. In the reference design, SPD0 and SPC0 pins are pulled up to LVDD (+3.3V) with 6.8k resistors. Through

these two pins, the internal register values of the chip can be read. The external Boot ROM can be updated if these

pins are connected to SPC1 and SPD1 with jumpers as shown in Figure 4.

• SPC1 and SPD1

SPD1 and SPC1 function as a serial interface where SPD1 is bi-directional data and SPC1 is an input only serial clock.

In the reference design, SPD1 and SPC1 pins are pulled up to LVDD (+3.3V) with 6.8kΩ resistors as shown in Figure

SPD1 and SPC1 are used to interface with the CH9904 (the serial Boot ROM). The CH7511B/7512B will auto-load

the values, such as EDIDs and configurations, etc., from the Boot ROM upon power-on or reset.

RE SETB

RE FCK

Figure 3: General Control Pins

VCC18

VCC33

10K

PMBS3904

RE SETB

10K

0.1 uF

PMBS3904

22p F

Y 1

27MHz

22p F

RE FCK

206-1000-014

AN-B014

RE SETB_ PCH

Rev. 1.7

2020-07-14