Chrontel CH7515A 레이아웃 디자인 매뉴얼 - 페이지 7
{카테고리_이름} Chrontel CH7515A에 대한 레이아웃 디자인 매뉴얼을 온라인으로 검색하거나 PDF를 다운로드하세요. Chrontel CH7515A 15 페이지.
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2.8
Other function pins
• GPIO [0:3]
These pins are general-purpose input/output. GPIO [0] should be connecting to VDDEN pin with jumper as shown in
Figure 8.
• BLUP, BLDN
BLUP is the increase backlight brightness input pin.
BLDN is the decrease backlight brightness input pin.
Buttons can be placed at these pins to adjust the backlight brightness. Design is shown in Figure 8.
• PWRDN
CH7515A enter into or exits power down state when receiving active low pulse from this pin. The connection is
shown in Figure 8.
SW2
C2
0.1uF
206-1000-021
Rev 1.0
J1
HEADER 3
3
SPDIF
U1
90
SCLK
89
WS
88
SDATA/SPDIF
87
MCLK
CH7515A
Figure 7: CH7515A IIS or SPDIF Output Pins
+3.3V
R1
10K
SW1
BLUP
R2
+3.3V
10K
C1
R3
0.1uF
10K
BLDN
+3.3V
R4
10K
R5
10K
SW3
PWRDN
R6
C3
10K
0.1uF
2020-07-15
2
1
I2S DAC
109
BLUP
108
BLDN
91
PWRDN
11
GPIO[0]
JP1
98
2
1
VDDEN
HEADER 1x2
CH7515A
AN-B021
U1
7