Alpha Data ADM-VPX3-9Z5-RTM 사용자 설명서 - 페이지 11

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ADM-VPX3-9Z5-RTM User Manual

V1.0 - 8th June 2021

3.4 LED Definitions

The position and description of the board status LED is shown in

Comp. Ref.

D3(Green)

D4(Green)

D5(Green)

3.5 JTAG Interface

3.5.1 On-board Interface

The JTAG boundary scan chain can be accessed via a standard header (J11).

This allows the connection of the Xilinx JTAG cable for FPGA debug and Flash programming via the Xilinx

toolchain.

3.5.2 JTAG Voltages

The Vcc supply provided to the JTAG cable on the config header is +3.3V and is protected by a poly fuse rated at

350mA.

Functional Description

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Function

Display Port 3.3V Supply Status

PSMIO31 LED

3.3V Supply Status

LED

D4 D5

Figure 4 : LED Locations

ON State

Normal operation

PSMIO=Logic Low

Normal operation

Table 3 : LED Definitions

Locations:

Off State

Fault

PSMIO=Logic High

Power Off

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