Digilent NetFPGA-SUME 참조 매뉴얼 - 페이지 12

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NetFPGA-SUME™ Reference Manual

FPGA Configuration

After power-on, the Virtex-7 FPGA must be configured (or programmed) before it can perform any functions. You

can configure the FPGA in one of two ways:



A PC can use the Digilent USB-JTAG circuitry (port J16, labeled "PROG") to program the FPGA any time the

power is on.



One of four bitstream files stored in the parallel flash can be loaded by the onboard CPLD.

Figure 12 above shows the different options available for configuring the FPGA. An on-board "mode" jumper (JP1)

selects between the two programming modes.

The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado

software from Xilinx can create bitstreams from VHDL, Verilog®, or schematic-based source files (in the ISE toolset,

EDK is used for MicroBlaze™ embedded processor-based designs).

Bitstreams are stored in SRAM-based memory cells within the FPGA. This data defines the FPGA's logic functions

and circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset

button attached to the PROG input, by writing a new configuration file using the JTAG port, or by triggering the

onboard CPLD to load a new bitstream from the parallel flash.

A Virtex-7 690T bitstream is typically 229,878,496 bits and can take a long time to transfer. The time it takes to

program the NetFPGA-SUME can be decreased by compressing the bitstream before programming, and then

allowing the FPGA to decompress the bitstream itself during configuration. Depending on design complexity,

compression ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools (ISE or

Vivado) to occur during generation. For instructions on how to do this, consult the Xilinx documentation for the

toolset being used.

After being successfully programmed, the FPGA will illuminate the "DONE" LED. Pressing the "PROG" button at any

time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately attempt to

reprogram itself from the parallel flash, assuming JP1 is not loaded.

Other product and company names mentioned may be trademarks of their respective owners.

Figure 12. NetFPGA-SUME configuration options.

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