MSI 612BF 매뉴얼 - 페이지 23

{카테고리_이름} MSI 612BF에 대한 매뉴얼을 온라인으로 검색하거나 PDF를 다운로드하세요. MSI 612BF 45 페이지. 3d-agp vga / 3d-audio m/b for socket 370
MSI 612BF에 대해서도 마찬가지입니다: 사용자 설명서 (48 페이지)

3-3 Advanced CHIPSET FEATURES SETUP

CMOS Setup Utility – Copyright © 1984 – 1998 Award Software
SDRAM CAS Latency Time
SDRAM Cycle Time Tras/Trc
SDRAM RAS-to-CAS Delay
SDRAM RAS Precharge Time
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
Delay Transaction
On-Chip Video Window Size
* Onboard Display Cache Setting *
CAS# Latency
Paging Mode Control
RAS-to-CAS Override
RAS# Timing
RAS# Precharge Timing Slow
Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit F1:General Help
F5:Previous Values F6:Optimal defaults F7:Standard Defaults
This section allows you to configure the system based on the specific features of the installed
chipset. This chipset manages bus speeds and access to system memory resources, such as
DRAM and the external cache. It also coordinates communications between the conventional
ISA bus and the PCI bus. It must be stated that these items should never need to be altered.
The default settings have been chosen because they provide the best operating conditions for
your system.
The only time you might consider making any changes would be if you
discovered that data was being lost while using your system.
DRAM Settings: The first chipset settings deal with CPU access to dynamic random
access memory (DRAM). The default timings have been carefully chosen and should only
be altered if data is being lost. Such a scenario might well occur if your system had mixed
speed DRAM chips installed so that greater delays may be required to preserve the
integrity of the data held in the slower memory chips.
SDRAM CAS Latency Time: When synchronous DRAM is installed, the number of clock
cycles of CAS latency depends on the DRAM timing.
The Choice: 2, 3
SDRAM Cycle Time Tras/Trc: Select the number of SCLKs for an access cycle.
The Choice:5/7,6/8.
SDRAM RAS-to-CAS Delay: This field lets you insert a timing delay between the CAS and
RAS strobe signals, used when DRAM is written to, read from, or refreshed. Fast gives
faster performance; and Slow gives more stable performance. This field applies only when
synchronous DRAM is installed in the system.
The Choice: 2, 3.
Advanced Chipset Features
3
6/8
3
3
Enabled
Enabled
Disabled
Enabled
64MB
3
Closed
Closed
Slow
22
Item Help
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