Toshiba TLP-510U 기술 교육 매뉴얼 - 페이지 41
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페이지 인쇄
7-5. Microprocessor Interface
The peripheral block diagram of the microprocessor
shows in Fig. 7-5-1. All kinds of control such as signal
SW, etc. are carried out by the I
level control of RGB signal process IC (QB024:
M52320SP) and the sync polarity information of the
sync process IC (QB012: M52347FP) are carried out in
QB025 (CXA1315M). Refer to table 7-5-1 for the logic
about the polarity information of sync signal.
From
Microprocessor
16
SCL
15
SDA
14
13
12
11
10
9
16
15
14
13
12
11
10
9
2
C of microprocessor. The
H. STATE
V. STATE
QB025
CXA1315M
Vcc
SW1
1
H. POL
SCL
SW0
2
V. POL
3
SDA
DAC4
R SUB CONTRAST
G SUB CONTRAST
SAD2
DAC3
4
SAD1
DAC2
5
B SUB CONTRAST
SAD0
DAC1
6
MAIN CONTRAST ADJUST
7
SW3
DAC0
BRIGHT ADJUST
SW2
GND
8
QV045
CXA1315M
Vcc
SW1
1
RGB/VIDEO
SW
SCL
SW0
2
3
SDA
DAC4
4
SAD2
DAC3
SAD1
DAC2
5
SAD0
DAC1
6
MUTE
7
VOL
SW3
DAC0
SW2
GND
8
ENABLE
SELECT
Fig. 7-5-1
RGB/VIDEO SW, Audio mute/volume adjustment, etc.
are controlled in QV045 (CXA1315M). Further, using
camera or not, camera zoom and focus adjustment
controls are carried out in QV057.
M52347FP
M52320SP
CS0
16
CS1
15
14
CS2
13
Vcc
FIL/SW
12
D7
VDET
11
D6
SYUSEN
10
D5
CAMON1
9
D4
PV013
7-14
QV057
M62320FP
SO
1
SCL
2
3
SDA
4
FOCUS +
D0
FOCUS -
D1
5
D2
6
ZOOM +
7
ZOOM -
D3
GND
8