Toshiba TLP710E 기술 교육 매뉴얼 - 페이지 29

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8 . CAMERA

OUT

(For TLP711)

The camera out circuit converts luminance color differ-

ence signals (Y/Pb/Pr) sent from a CCD camera into a

standard video signal in a format of the NTSC or PAL

system. Moreover, this circuit also bypasses the CCD

camera signal to the main unit side.

8-1. Signal Input Circuit

The luminance color difference signals (Y/Pb/Pr), H

(horizontal sync signal), and V (vertical sync signal)

enter the input circuit from the CCD camera.

Each signal level is as follows.

Y :

1.2 V(p-p) + 1.2V (DC bias)

Pb/Pr: 1.2 V(p-p) + 0.6V (DC bias)

H/V:

3 V(p-p)

The signal input circuit converts the signal levels as

shown below, required for the camera output circuit and

the main unit circuit.

< Camera out >

Y :

2.0 V(p-p)

Pb/Pr: 2.0 V(p-p)

H/V:

5 V(p-p)

8-2. A/D Converter

The A/D converter in one chip has 3 inputs and accepts

each of Y, Pb, and Pr signal. It also 3 channels for the

digital output ports. But in the circuit, 2 channels are

used to convert the data in a format called 4:2:2 format.

In the 4:2:2 format, each pixel data for the luminance

color difference signal (Y/Pb/Pr) is assumed as pixel 0

(Y0/Pb0/Pr0), pixel 1 (Y1/Pb1,Pr1), ......, one channel

→ Y1 → Y2 → Y3, and the other channel

develops Y0

→ Pr0 → Pb2 → Pr2. That is, each of Pb

develops Pb0

and Pr is output by 2 pixels at every two pixels to 4

p i x e l s f o r Y .

The A/D converter contains a clamp circuit and the

signals are clamped with the clamp signal sent from the

PLD. The reference voltages for the A/D are made by

QH350 and set to within 1.5V – 3.5V.

CIRCUIT

< Main unit >

Y :

0.7 V(p-p)

Pb/Pr: 0.7 V(p-p)

H/V:

5 V(p-p)

8-3. P L D

The PLD controls all of the digital signal processes such as

timings for the A/D converter, NTSC/PAL encoder, PLL

control, memory control, picture format conversion, etc.

The signal systems and their effective areas for the

signals developed in the camera out circuit are as follows:

NTSC: 720 samples in H direction, 480 lines in

V direction (interlace)

PAL:

680 samples in H direction, 512 lines in

V direction (interlace)

On the other hand, as the CCD camera signal has XGA

resolution of 1024 samples in H direction and 768 lines

in V direction, some of them are skipped when storing in

the memory. In the NTSC system, 3 of 8 are skipped to

obtain 480 lines and in the PAL, 1 of 3 is skipped to

obtain 512 lines.

Moreover, a serial data in 4:2:2 format is sent to the

NTSC/PAL encoder. Each signal is in the order of Pb0

→ Pr0 → Y1 → Pb2 → Y2 → Pr2 → Y3 → in 4:2:2

format.

The NTSC and PAL mode are determined by logic of

SH001 (2p). In the logic L, the mode is set to the NTSC

and in the H the mode is PAL. This logic is read in the

main microprocessor through the I

8-4. NTSC/PAL Encoder

The encoder contains a D/A converter and converts the

4:2:2 format serial data sent from the PLD into the NTSC

or PAL format composite signal. Switching of the NTSC

or PAL is determined by the logic of SH001 shown above

and controlled by the main microprocessor through the

C bus.

8-5. Signal Output Circuit

This circuit consists of the circuit which adjusts the

NTSC or PAL format composite signal sent from the

encoder to a specified level and a driver with 75-ohm

impedance. The 75-ohm driver consists of QH602 and

contains a sag reduction circuit. Sags are eliminated by

the capacitor CH607.

8-1

→

C bus via QH700.