Cypress CE219490 사용자 설명서 - 페이지 2

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Design and Implementation

This design consists of a PWM resource and a Smart I/O resource, both creating square waves of slightly different frequencies.

These square waves are routed through an exclusive-OR (XOR) gate within the Smart I/O resource, yielding a signal with a

gradually changing duty cycle. The rate of change is proportional to the difference between the output square wave frequencies.

The signal is then output to I/O4 of the Smart I/O port 9. Driving LED with this signal results in a "ramping" effect, where the LED

gradually get brighter and dimmer alternately.

The PWM is driven by a 10-kHz clock with a period of 399 counts and a compare value of 200 counts. This gives a 50 percent

duty cycle square wave with a 40-ms period. The Smart I/O is clocked at 99 Hz using a divided clock sourced from CLK_PERI.

This input clock is divided by 4 using the lookup tables (LUTs) of the Smart I/O resource to produce a square wave with a

40.4-ms period.

To generate a square wave signal with a time period close to 40 ms, a 99-Hz clock is divided by 4 using a synchronous sequential

circuit, which is realized using the LUTs of the Smart I/O resource.

To implement a divide-by-4 sequential circuit, consider the state transition values shown in

From this state transition table, you can observe that Q0 is half the frequency of Clk_SmartIO and Q1 is 1/4

Clk_SmartIO. This sequential logic can be implemented using the LUTs of the Smart I/O resource.

Figure 1

shows the implementation of this logic using LUT 2 and LUT 3. In addition, the divided clock is XORed with the PWM

output using LUT 4 to generate a signal with the duty cycle gradually increasing and decreasing over time. The output of LUT 4

is driven to I/O 4 output.

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Table 1. State Transition Table for a Divide-by-4 Sequential Circuit

Present State

CLK

Document No. 002-25568 Rev.*A

PSoC 6 MCU Ramping LED using Smart I/O

Next State

Table 1:

frequency of