Cypress CY3274 애플리케이션 노트 - 페이지 5

{카테고리_이름} Cypress CY3274에 대한 애플리케이션 노트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress CY3274 19 페이지. Powerline communication board design analysis
Cypress CY3274에 대해서도 마찬가지입니다: 빠른 시작 매뉴얼 (2 페이지)

페이지 인쇄

2.1

Transmit Signal Path

2 . 1 . 1

T r a n s m i t F i l t e r

The FSK transmit signal TX is generated on the FSK_OUT pin of the Cypress PLC device as a low amplitude

(~125 mVp-p), unfiltered signal. This signal is applied to the input of an external transmit filter block consisting of

opamps U2 and U3, and their related passive components. The transmit filter is a fourth order Chebyshev response

band pass filter, designed for 1.5 dB maximum pass band ripple. It provides 16.5 dB of gain at the center frequency

of 133 kHz, suppression of -20 dBc at the 150 kHz band limit, and -50 dBc and -60 dBc at the second and third

carrier harmonics, respectively. The transmit filter response is shown graphically in

The power supply for the transmit filter opamps is a filtered version of the VPWR supply. This prevents the relatively

large currents produced by the power amplifier from feeding back into the high-Q filter circuit through the power

supply and causing oscillations. Hence, it is advisable to avoid routing the high current transmit signal near the filter

circuit.

2 . 1 . 2

T r a n s m i t Am p l i f i c a t i o n

The filtered transmit data signal is applied to the power amplifier, which consists of opamp U4, transistors Q1 and Q2,

and associated passive components. The power amplifier provides an additional 12 dB voltage gain, and is capable

of driving low impedance loads presented by the powerline.

2 . 1 . 3

H i g h V o l t a g e C o u p l i n g

The transmit signal from the power amplifier is driven on to the powerlines via the isolation transformer T1. Capacitor

C14 provides DC isolation for the transmitter on the device side, and C9 provides line frequency isolation on the line

side.

When the device is not actively transmitting, the signal TX_DISABLE is asserted from the PLC device. This disables

the external power amplification circuitry to save power and make the transmit amplification circuit have a high

impedance so that the receive signal is not attenuated. Note that the transmit filter stage amplifiers U2 and U3 are

always enabled, so that there is no spurious noise output on the line due to filter ringing at startup.

www.cypress.com

Figure 3. Cypress High Voltage PLC Board Transmit Filter Response

Document No. 001-55427 Rev. *E

Cypress Powerline Communication Board Design Analysis

Figure