Cypress 7C185-15 사양 시트

{카테고리_이름} Cypress 7C185-15에 대한 사양 시트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress 7C185-15 12 페이지. 8k x 8 static ram

페이지 인쇄
Features
• High speed
— 15 ns
• Fast t
DOE
• Low active power
— 715 mW
• Low standby power
— 220 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY7C185 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CE
1
CE
2
WE
OE
[2]
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Note:
1.
For guidelines on SRAM system design, please refer to the 'System Design Guidelines' Cypress application note, available on the internet at www.cypress.com.
2.
For military specifications, see the CY7C185A data sheet.
Cypress Semiconductor Corporation
Document #: 38-05043 Rev. *A
, CE
, and OE features
1
2
[1]
INPUT BUFFER
256 x 32 x 8
ARRAY
POWER
DOWN
COLUMN DECODER
7C185-15
130
40/15
•
3901 North First Street
provided by an active LOW chip enable (CE
chip enable (CE
three-state drivers. This device has an automatic power-down
feature (CE
or CE
1
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE
puts are both LOW and CE
input/output pins (I/O
location addressed by the address present on the address
pins (A
through A
0
selecting the device and enabling the outputs, CE
active LOW, CE
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins are present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
7C185-20
15
20
110
20/15
•
San Jose
8K x 8 Static RAM
), and active LOW output enable (OE) and
2
), reducing the power consumption by 70%
2
is HIGH, data on the eight data
2
through I/O
) is written into the memory
0
7
). Reading the device is accomplished by
12
active HIGH, while WE remains inactive or
2

Pin Configurations

DIP/SOJ/SOIC
Top View
NC
1
A
2
4
A
3
5
A
6
4
A
5
7
A
6
8
A
9
7
A
10
8
A
11
9
A
12
10
I/O
0
11
I/O
1
12
I/O
2
13
GND
14
7C185-25
25
100
20/15
•
CA 95134
•
Revised September 13, 2002
CY7C185
), an active HIGH
1
and WE in-
1
and OE
1
V
28
CC
WE
27
CE
26
2
A
25
3
A
24
2
A
23
1
OE
22
A
21
0
CE
20
1
I/O
19
7
I/O
18
6
I/O
17
5
I/O
16
4
I/O
15
3
7C185-35
35
100
20/15
408-943-2600