Cypress Semiconductor CY2291 사양 시트 - 페이지 6
{카테고리_이름} Cypress Semiconductor CY2291에 대한 사양 시트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress Semiconductor CY2291 12 페이지. Cypress three-pll general purpose eprom programmable clock generator specification sheet
페이지 인쇄Electrical Characteristics, Industrial 3.3V
Parameter
Description
V
HIGH-Level Input Voltage
IH
V
LOW-Level Input Voltage
IL
I
Input HIGH Current
IH
I
Input LOW Current
IL
I
Output Leakage Current
OZ
I
V
Supply Current
DD
DD
Industrial
I
V
Power Supply Current
DDS
DD
in Shutdown Mode
I
V
Power Supply Current V
BATT
BATT
Switching Characteristics, Commercial 5.0V
Parameter
Name
t
Output Period
1
Output Duty
[11]
Cycle
t
Rise Time
3
t
Fall Time
4
t
Output Disable
5
Time
t
Output Enable
6
Time
t
Skew
7
t
CPUCLK Slew
8
[14]
t
Clock Jitter
9A
[14]
t
Clock Jitter
9B
[14]
t
Clock Jitter
9C
[14]
t
Clock Jitter
9D
t
Lock Time for
10A
CPLL
Notes
11. XBUF duty cycle depends on XTALIN duty cycle.
12. Measured at 1.4V.
13. Measured between 0.4V and 2.4V.
14. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application
note: "Jitter in PLL-Based Systems."
15. CLKF is not guaranteed to be in phase with CLKA-D, even if it is referenced off the same PLL.
Document #: 38-07189 Rev. *C
(continued)
Conditions
[9]
Except crystal pins
[9]
Except crystal pins
V
= V
–0.5V
IN
DD
V
= +0.5V
IN
Three-state outputs
[10]
V
= V
max., 3.3V operation
DD
DD
Shutdown active,
[10]
excluding V
BATT
= 3.0V
BATT
Description
Clock output range, 5V
operation
Duty cycle for outputs, defined as t
f
> 66 MHZ
OUT
Duty cycle for outputs, defined as t
f
< 66 MHZ
OUT
[13]
Output clock rise time
[13]
Output clock fall time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related outputs
12, 15]
Frequency transition rate
Peak-to-peak period jitter (t
9A
clock period (f
< 4 MHz)
OUT
Peak-to-peak period jitter (t
9B
(4 MHz < f
< 16 MHz)
OUT
Peak-to-peak period jitter
(16 MHz < f
< 50 MHz)
OUT
Peak-to-peak period jitter
(f
> 50 MHz)
OUT
Lock Time from Power Up
Min.
CY2291I/CY2291FI
CY2291
(100 MHz)
CY2291F
(90 MHz)
÷ t
[12]
2
1
÷ t
[12]
2
1
[3,
Max. – t
min.),% of
9A
Max. – t
min.)
9B
CY2291
Typ.
Max.
2.0
0.8
< 1
10
< 1
10
250
50
70
10
100
5
15
Min.
Typ.
Max.
10
13000
(76.923 kHz)
11.1
13000
(76.923 kHz)
40%
50%
60%
45%
50%
55%
3
5
2.5
4
10
15
10
15
< 0.25
0.5
1.0
20.0
< 0.5
1
< 0.7
1
< 400
500
< 250
350
< 25
50
Page 6 of 12
Unit
V
V
μA
μA
μA
mA
μA
μA
Unit
ns
ns
ns
ns
ns
ns
ns
MHz/m
s
%
ns
ps
ps
ms
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