Cypress Semiconductor CY62148EV30 사양 시트
{카테고리_이름} Cypress Semiconductor CY62148EV30에 대한 사양 시트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress Semiconductor CY62148EV30 13 페이지. Mobl 4-mbit (512k x 8) static ram
페이지 인쇄Features
Very high speed: 45 ns
■
Wide voltage range: 2.20V to 3.60V
❐
Temperature ranges
■
Industrial: –40°C to +85°C
❐
Automotive-A: –40°C to +85°C
❐
Pin compatible with CY62148DV30
■
Ultra low standby power
■
Typical standby current: 1 μA
❐
Maximum standby current: 7 μA (Industrial)
❐
Ultra low active power
■
Typical active current: 2 mA at f = 1 MHz
❐
Easy memory expansion with CE, and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Available in Pb-free 36-ball VFBGA, 32-pin TSOP II and 32-pin
■
[1]
SOIC
packages
Logic Block Diagram
CE
WE
OE
Notes
1. SOIC package is available only in 55 ns speed bin.
2. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05576 Rev. *G
A 0
INPUT BUFFER
A 1
A 2
A 3
A 4
A 5
A 6
512K x 8
A 7
A 8
ARRAY
A 9
A 10
A 11
A 12
COLUMN DECODER
•
198 Champion Court
4-Mbit (512K x 8) Static RAM
Functional Description
[2]
The CY62148EV30
is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption by more than 99 percent when deselected
(CE HIGH). The eight input and output pins (IO
placed in a high impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight IO pins (IO
then written into the location specified on the address pins (A
through A
).
18
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the IO pins.
POWER
DOWN
,
•
San Jose
CA 95134-1709
®
MoBL
CY62148EV30
®
) in portable
through IO
0
through IO
0
IO 0
IO 1
IO 2
IO 3
IO 4
IO 5
IO 6
IO 7
•
408-943-2600
Revised August 4, 2008
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7
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7
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