Cypress Semiconductor CY62157CV33 사양 시트 - 페이지 5
{카테고리_이름} Cypress Semiconductor CY62157CV33에 대한 사양 시트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress Semiconductor CY62157CV33 14 페이지. 512k x 16 static ram
페이지 인쇄[7]
Capacitance
Parameter
C
Input Capacitance
IN
C
Output Capacitance
OUT
AC Test Loads and Waveforms
V
CC
OUTPUT
INCLUDING
JIG AND
SCOPE
Parameters
R1
R2
R
TH
V
TH
Data Retention Characteristics
Parameter
Description
V
V
for Data Retention
DR
CC
I
Data Retention Current
CCDR
[8]
t
Chip Deselect to Data
CDR
Retention Time
[8]
t
Operation Recovery Time
R
Data Retention Waveform
V
CC
CE
or
1
BHE.BLE
or
CE
2
Notes:
8. Full Device AC operation requires linear V
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05014 Rev. *F
Description
T
V
R1
V
CC
R2
30 pF
Rise TIme: 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
3.0V
1.105
1.550
0.645
1.75
(Over the Operating Range)
V
= 1.5V, CE
CC
CE
< 0.2V,
2
V
> V
– 0.2V or V
IN
CC
[9]
V
CC(min.)
t
CDR
ramp from V
to V
CC
DR
CC(min.)
Test Conditions
= 25°C, f = 1 MHz,
A
= V
CC
CC(typ.)
ALL INPUT PULSES
Typ
90%
10%
GND
R
TH
V
TH
3.3V
1.216
1.374
0.645
1.75
Conditions
> V
– 0.2V or
Auto-A
1
CC
Auto-E
< 0.2V
IN
DATA RETENTION MODE
V
> 1.5 V
DR
> 100 µs or stable at V
>100 µs.
CC(min.)
CY62157CV30/33
Max.
Unit
6
pF
8
pF
90%
10%
Fall Time: 1 V/ns
Unit
ΚΩ
ΚΩ
ΚΩ
V
[2]
Min.
Typ.
Max.
Unit
1.5
4
20
4
60
0
t
RC
V
CC(min.)
t
R
Page 5 of 13
V
µA
µA
ns
ns
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