Cypress Semiconductor CY7C1012DV33 사양 시트 - 페이지 5

{카테고리_이름} Cypress Semiconductor CY7C1012DV33에 대한 사양 시트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress Semiconductor CY7C1012DV33 12 페이지. 12-mbit (512k x 24) static ram

페이지 인쇄
AC Switching Characteristics
[5]
Over the Operating Range
Parameter
Read Cycle
[6]
t
V
power
CC
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE Active LOW to Data Valid
ACE
t
OE LOW to Data Valid
DOE
t
OE LOW to Low Z
LZOE
t
OE HIGH to High Z
HZOE
t
CE Active LOW to Low Z
LZCE
t
CE Deselect HIGH to High Z
HZCE
t
CE Active LOW to Power Up
PU
t
CE Deselect HIGH to Power Down
PD
[9, 10]
Write Cycle
t
Write Cycle Time
WC
t
CE Active LOW to Write End
SCE
t
Address Setup to Write End
AW
t
Address Hold from Write End
HA
t
Address Setup to Write Start
SA
t
WE Pulse Width
PWE
t
Data Setup to Write End
SD
t
Data Hold from Write End
HD
t
WE HIGH to Low Z
LZWE
t
WE LOW to High Z
HZWE
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in part a) of
6. t
gives the minimum amount of time that the power supply is at typical V
POWER
7. t
, t
, t
, t
, t
, and t
HZOE
HZCE
HZWE
LZOE
LZCE
voltage.
8. These parameters are guaranteed by design and are not tested.
9. The internal write time of the memory is defined by the overlap of CE
a write. The transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates
the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
Document Number: 38-05610 Rev. *D
Description
(Typical) to the First Access
[3]
[7]
[7]
[3, 7]
[3, 7]
[3, 8]
[3]
[7]
[7]
Figure
2, unless specified otherwise.
are specified with a load capacitance of 5 pF as in part (b) of
LZWE
or CE
1
[3, 8]
values until the first memory access is performed.
CC
Figure
or CE
LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate
2
3
and t
.
HZWE
SD
CY7C1012DV33
–10
Min
Max
100
10
10
3
10
5
1
5
3
5
0
10
10
7
7
0
0
7
5.5
0
3
5
2. Transition is measured ±200 mV from steady state
Page 5 of 11
Unit
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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