Cypress Semiconductor CY7C1297H 사양 시트 - 페이지 5

{카테고리_이름} Cypress Semiconductor CY7C1297H에 대한 사양 시트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress Semiconductor CY7C1297H 16 페이지. Cypress 1-mbit (64k x 18) flow-through sync sram specification sheet

페이지 인쇄
ZZ Mode Electrical Characteristics
Parameter
I
Sleep mode standby current
DDZZ
t
Device operation to ZZ
ZZS
t
ZZ recovery time
ZZREC
t
ZZ Active to sleep current
ZZI
t
ZZ Inactive to exit sleep current
RZZI
[2, 3, 4, 5, 6]

Truth Table

Cycle Description
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Sleep Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
2. X = "Don't Care." H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW
BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05669 Rev. *B
Description
Address Used CE
CE
1
2
None
H
X
None
L
L
None
L
X
None
L
L
None
X
X
None
X
X
External
L
H
External
L
H
External
L
H
External
L
H
External
L
H
Next
X
X
Next
X
X
Next
H
X
Next
H
X
Next
X
X
Next
H
X
Current
X
X
Current
X
X
Current
H
X
Current
H
X
Current
X
X
Current
H
X
, BW
A
B
Test Conditions
ZZ > V
– 0.2V
DD
ZZ > V
– 0.2V
DD
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
CE
ZZ ADSP
ADSC
ADV WRITE OE
3
X
L
X
L
X
L
L
X
H
L
L
X
X
L
H
L
X
L
H
L
X
H
X
X
L
L
L
X
L
L
L
X
L
L
H
L
L
L
H
L
L
L
H
L
X
L
H
H
X
L
H
H
X
L
X
H
X
L
X
H
X
L
H
H
X
L
X
H
X
L
H
H
X
L
H
H
X
L
X
H
X
L
X
H
X
L
H
H
X
L
X
H
) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BW
[A: B]
CY7C1297H
Min.
Max.
40
2t
CYC
2t
CYC
2t
CYC
0
CLK
X
X
X
L-H
Tri-State
X
X
X
L-H
Tri-State
X
X
X
L-H
Tri-State
X
X
X
L-H
Tri-State
X
X
X
L-H
Tri-State
X
X
X
X
Tri-State
X
X
L
L-H
X
X
H
L-H
Tri-State
X
L
X
L-H
X
H
L
L-H
X
H
H
L-H
Tri-State
L
H
L
L-H
L
H
H
L-H
Tri-State
L
H
L
L-H
L
H
H
L-H
Tri-State
L
L
X
L-H
L
L
X
L-H
H
H
L
L-H
H
H
H
L-H
Tri-State
H
H
L
L-H
H
H
H
L-H
Tri-State
H
L
X
L-H
H
L
X
L-H
. Writes may occur only on subsequent clocks
Page 5 of 15
Unit
mA
ns
ns
ns
ns
DQ
Q
D
Q
Q
Q
D
D
Q
Q
D
D
, BW
),
A
B
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