Cypress Semiconductor CY7C1306BV25 사양 시트 - 페이지 11
{카테고리_이름} Cypress Semiconductor CY7C1306BV25에 대한 사양 시트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress Semiconductor CY7C1306BV25 20 페이지. Cypress 18-mbit burst of 2 pipelined sram with qdr architecture specification sheet
페이지 인쇄
TAP Controller Block Diagram
Selection
TDI
Circuitry
TCK
TMS
TAP Electrical Characteristics
Parameter
Description
V
Output HIGH Voltage
OH1
V
Output HIGH Voltage
OH2
V
Output LOW Voltage
OL1
V
Output LOW Voltage
OL2
V
Input HIGH Voltage
IH
V
Input LOW Voltage
IL
I
Input and Output Load Current
X
TAP AC Switching Characteristics
Parameter
t
TCK Clock Cycle Time
TCYC
t
TCK Clock Frequency
TF
t
TCK Clock HIGH
TH
t
TCK Clock LOW
TL
Set-up Times
t
TMS Set-up to TCK Clock Rise
TMSS
t
TDI Set-up to TCK clock Rise
TDIS
t
Capture Set-up to TCK Rise
CS
Hold Times
t
TMS Hold after TCK Clock Rise
TMSH
t
TDI Hold after Clock Rise
TDIH
t
Capture Hold after Clock Rise
CH
Notes:
10. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
11. t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
12. Test conditions are specified using the load in TAP AC test conditions. t
Document #: 38-05627 Rev. *A
Instruction Register
29
31
30
.
.
Identification Register
.
106
.
.
.
Boundary Scan Register
TAP Controller
[10, 14, 17]
Over the Operating Range
Test Conditions
= −2.0 mA
I
OH
= −100 µA
I
OH
I
= 2.0 mA
OL
= 100 µA
I
OL
GND ≤ V
≤ V
I
DDQ
Over the Operating Range
Description
/t
= 1 ns.
R
F
0
Bypass Register
Selection
2
1
0
Circuitry
2
1
0
2
1
0
Min.
1.7
2.1
1.7
–0.3
−5
[11, 12]
Min.
50
20
20
10
10
10
10
10
10
CY7C1303BV25
CY7C1306BV25
TDO
Max.
Unit
V
V
0.7
V
0.2
V
V
+ 0.3
V
DD
0.7
V
µA
5
Max.
Unit
ns
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
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