Cypress Semiconductor MoBL CY62157E 사양 시트
{카테고리_이름} Cypress Semiconductor MoBL CY62157E에 대한 사양 시트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress Semiconductor MoBL CY62157E 12 페이지. 8-mbit (512k x 16) static ram
페이지 인쇄Features
• Very high speed: 45 ns
• Wide voltage range: 4.5V–5.5V
• Ultra-low standby power
—Typical Standby current: 2 µA
—Maximum Standby current: 8 µA (Industrial)
• Ultra-low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Ultra-low standby power
• Easy memory expansion with CE
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
package
Functional Description
The CY62157E is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
Logic Block Diagram
Note:
1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05695 Rev. *C
, CE
and OE features
1
2
[1]
®
) in
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
512K x 16
A
5
RAM Array
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
POWER-DOWN
CIRCUIT
•
198 Champion Court
8-Mbit (512K x 16) Static RAM
also has an automatic power-down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
deselected (CE
HIGH or CE
1
2
HIGH). The input/output pins (IO
a high-impedance state when: deselected (CE
LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE
LOW and CE
HIGH) and Write Enable (WE) input LOW.
1
2
If Byte Low Enable (BLE) is LOW, then data from IO pins (IO
through IO
), is written into the location specified on the
7
address pins (A
through A
0
18
LOW, then data from IO pins (IO
the location specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE
LOW and CE
HIGH) and Output Enable (OE)
1
2
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on IO
High Enable (BHE) is LOW, then data from memory will appear
on IO
to IO
. See the truth table at the back of this data sheet
8
15
for a complete description of read and write modes.
IO
–IO
0
IO
–IO
8
BHE
WE
OE
BLE
BHE
BLE
,
•
San Jose
CA 95134-1709
CY62157E MoBL
LOW or both BHE and BLE are
through IO
) are placed in
0
15
HIGH or CE
1
LOW, CE
HIGH and WE
1
2
). If Byte High Enable (BHE) is
through IO
) is written into
8
15
through A
).
0
18
to IO
. If Byte
0
7
7
15
CE
2
CE
1
CE
2
CE
1
•
408-943-2600
Revised November 21, 2006
®
2
0
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